v2.7
Axcelerator Family FPGAs
u
e
–
Voltage-Referenced I/O Standards: GTL+, HSTL
Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2
Registered I/Os
Hot-Swap Compliant I/Os (except PCI)
Programmable Slew Rate and Drive Strength on
Outputs
Leading-Edge Performance
•
•
•
•
350+ MHz System Performance
500+ MHz Internal Performance
High-Performance Embedded FIFOs
700 Mb/s LVDS Capable I/Os
–
–
–
Specifications
–
Programmable Delay and Weak Pull-Up/Pull-Down
Circuits on Inputs
•
•
•
•
•
Up to 2 Million Equivalent System Gates
Up to 684 I/Os
Up to 10,752 Dedicated Flip-Flops
Up to 295 kbits Embedded SRAM/FIFO
Manufactured on Advanced 0.15 μm CMOS Antifuse
Process Technology, 7 Layers of Metal
•
Embedded Memory:
–
Variable-Aspect 4,608-bit RAM Blocks (x1, x2, x4,
x9, x18, x36 Organizations Available)
Independent, Width-Configurable Read and Write Ports
Programmable Embedded FIFO Control Logic
–
–
•
•
Segmentable Clock Resources
Embedded Phase-Locked Loop:
Features
•
•
•
•
•
Single-Chip, Nonvolatile Solution
–
–
14-200 MHz Input Range
Frequency Synthesis Capabilities up to 1 GHz
Up to 100% Resource Utilization with 100% Pin Locking
1.5V Core Voltage for Low Power
Footprint Compatible Packaging
•
•
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Debug Capability
with Actel Silicon Explorer II
Flexible, Multi-Standard I/Os:
–
–
–
1.5V, 1.8V, 2.5V, 3.3V Mixed Voltage Operation
Bank-Selectable I/Os – 8 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3V
PCI, and 3.3V PCI-X
•
•
Boundary-Scan Testing Compliant with IEEE Standard
1149.1 (JTAG)
FuseLockTM Secure Programming Technology
Prevents Reverse Engineering and Design Theft
–
Differential I/O Standards: LVPECL and LVDS
Table 1-1 • Axcelerator Family Product Profile
Device
AX125
125,000
82,000
AX250
250,000
154,000
AX500
500,000
286,000
AX1000
1,000,000
612,000
AX2000
2,000,000
1,060,000
Capacity (in Equivalent System Gates)
Typical Gates
Modules
Register (R-cells)
Combinatorial (C-cells)
Maximum Flip-Flops
Embedded RAM/FIFO
Number of Core RAM Blocks
Total Bits of Core RAM
Clocks (Segmentable)
Hardwired
672
1,344
1,344
1,408
2,816
2,816
2,688
5,376
5,376
6,048
12,096
12,096
10,752
21,504
21,504
4
12
55,296
16
73,728
36
165,888
64
294,912
18,432
4
4
8
4
4
8
4
4
8
4
4
8
4
4
8
Routed
PLLs
I/Os
I/O Banks
8
8
8
8
8
Maximum User I/Os
Maximum LVDS Channels
Total I/O Registers
Package
168
84
504
248
124
744
336
168
1,008
516
258
1,548
684
342
2,052
CSP
180
PQFP
208
208
BGA
FBGA
CQFP
729
484, 676, 896
352
256, 324
256, 484
208, 352
484, 676
208, 352
896, 1152
352
CCGA
624
624
November 2008
i
© 2008 Actel Corporation
*See Actel’s website for the latest version of the datasheet.
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