Philips Semiconductors
Application note
AU5790 Single wire CAN transceiver
AN2005
Table 3. Power Dissipation At 13.4 V Battery Voltage Vs. Node Count
I
P
V
I
I
I
P
P
tot
BATPN
(mA)
PNINT
CANHN
(V)
LOADN
(mA)
BATN
INT
INT
Nodes
R
(Ω)
V
(V)
Dcycle
L
BAT
(mW)
26.8
26.8
26.8
26.8
(mA)
(mA)
(mW)
263.5
298.9
343.1
396.2
(mW)
145.1
162.8
184.9
211.5
2
4550
13.4
13.4
13.4
13.4
2
2
2
2
4.55
4.55
4.55
4.55
1
5
20
19
0.5
0.5
0.5
0.5
10
20
32
910
455
24
19
10
16
29
19
284.4
35
19
Table 4. Power Dissipation At 18 V Battery Voltage Vs. Node Count
R
I
P
(mW)
V
I
I
I
P
P
tot
L
BATPN
(mA)
PNINT
CANHN
(V)
LOADN
(mA)
BATN
INT
INT
Nodes
V
(V)
Dcycle
BAT
(Ω)
4550
910
(mA)
(mA)
(mW)
355.5
409.3
476.5
557.2
(mW)
195.7
222.6
256.3
296.6
2
18
18
18
18
2
2
2
2
36
4.55
4.55
4.55
4.55
1
5
20
19
0.5
0.5
0.5
0.5
10
20
32
36
24
19
455
36
10
16
29
19
284.4
36
35
19
Table 5. Power Dissipation At 26.5 V Battery Voltage Vs. Node Count
R
I
P
(mW)
V
I
I
I
P
P
tot
L
BATPN
(mA)
PNINT
CANHN
(V)
LOADN
(mA)
BATN
INT
INT
Nodes
V
(V)
Dcycle
BAT
(Ω)
4550
910
455
284
(mA)
(mA)
(mW)
525.5
613.3
723
(mW)
289.2
333.1
388
2
26.5
26.5
26.5
26.5
2
2
2
2
53
4.55
4.55
4.55
4.55
1
5
20
19
0.5
0.5
0.5
0.5
10
20
32
53
24
19
53
10
16
29
19
53
35
19
854.7
453.8
4.3.3 Selecting a Package and Board
In a user’s application, the following are usually known or can be calculated from circuit parameters;
Tj(max) = 150 _C from the data sheet.
This is the maximum allowed junction temperature.
Ta(max) is known from the user’s application.
Typically the maximum ambient temperature, Ta, it will be 85 _C for most body multiplexing nodes, however some nodes such as those
in the instrument cluster may require operation at 105 _C and any nodes in the engine compartment will most likely require operation in
a 125 _C ambient.
Pd(max) is the power dissipation for the worst case combination of load and supply voltage.
It can be calculated as described in the previous section for any application. Several summaries of calculated Pd are shown in Tables 3,
4, and 5 at the end of the previous section.
This leaves only the thermal resistance, θja, as an unknown. The thermal equation can be solved for θja.
Tj = Ta + Pd*θja Becomes; θja = (Tj–Ta)/Pd
With θja calculated, Figures 14 and 15 may be used to determine a package and PC board configuration that will provide a thermal resistance,
θja, less than the required value.
For example assume; θja(max) = 125 _C/W
Examining Figure 14 for the SO-8 package we find that a high conductance board with just the normal signal traces will provide approximately
100 _C/W and hence exceeds the requirements with margin to spare. The low conductance board will also work if 225-sq. mm of foil area is
included on pin 8, the fused pin, to act as a heat sink providing approximately 120 _C/W. It can also be seen that the very low thermal
conductance board will not support this application using an SO-8 package. If we now examine the SO-14 curves in Figure 15 we find even the
very low conductance board will meet the needs of the application with minimal additional copper foil for heat dissipation, and the low and high
conductance boards do not require any extra foil area.
For selected operating voltages Figures 17 through 22 shows plots that allow the user to select a board type if the number of standard nodes,
operating voltage, and ambient temperature are known. These plots were created using the data and equations from the previous two sections.
Select the plot for the operating voltage and package type being considered, and then find the intersection of the maximum node count and the
highest ambient temperature required. Any curve which is above the intersection point represents a board type and possible area of heat
dissipating copper foil which will provide a low enough thermal resistance to meet the applications needs. These plots assume all nodes use the
normal unit load resistance of 9.1 kΩ, and insure that the junction temperature, Tj, will not exceed 150 _C.
19
2001 Apr 16
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