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ATXMEGA128A3U-AU PDF预览

ATXMEGA128A3U-AU

更新时间: 2024-01-29 20:36:16
品牌 Logo 应用领域
爱特美尔 - ATMEL 微控制器
页数 文件大小 规格书
116页 4095K
描述
8/16-bit Atmel XMEGA A3U Microcontroller

ATXMEGA128A3U-AU 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:HVQCCN,
Reach Compliance Code:compliant风险等级:5.31
具有ADC:YES其他特性:IT IS ALSO OPERATES IN 12 MHZ AT 1.6 V
地址总线宽度:位大小:16
最大时钟频率:16 MHzDAC 通道:YES
DMA 通道:YES外部数据总线宽度:
JESD-30 代码:S-XQCC-N64长度:9 mm
I/O 线路数量:50端子数量:64
PWM 通道:YES封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
ROM可编程性:FLASH座面最大高度:1 mm
速度:32 MHz最大供电电压:3.6 V
最小供电电压:2.7 V标称供电电压:3 V
表面贴装:YES技术:CMOS
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:9 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER, RISC

ATXMEGA128A3U-AU 数据手册

 浏览型号ATXMEGA128A3U-AU的Datasheet PDF文件第4页浏览型号ATXMEGA128A3U-AU的Datasheet PDF文件第5页浏览型号ATXMEGA128A3U-AU的Datasheet PDF文件第6页浏览型号ATXMEGA128A3U-AU的Datasheet PDF文件第8页浏览型号ATXMEGA128A3U-AU的Datasheet PDF文件第9页浏览型号ATXMEGA128A3U-AU的Datasheet PDF文件第10页 
XMEGA A3U  
6. AVR CPU  
6.1  
Features  
8/16-bit high performance AVR RISC Architecture  
– 142 instructions  
– Hardware multiplier  
32x8-bit registers directly connected to the ALU  
Stack in SRAM  
Stack Pointer accessible in I/O memory space  
Direct addressing of up to 16Mbytes of program and 16Mbytes of data memory  
True 16/24-bit access to 16/24-bit I/O registers  
Support for 8-, 16- and 32-bit Arithmetic  
Configuration Change Protection of system critical features  
6.2  
Overview  
The Atmel® AVR® XMEGA® devices use the 8/16-bit AVR CPU. The main function of the CPU is  
to execute the code and perform all calculations. The CPU is able to access memories, perform  
calculations, control peripherals, and execute the program from the FLASH memory. Interrupt  
handling is described in a separate section, refer to ”Interrupts and Programmable Multi-level  
Interrupt Controller” on page 26.  
Figure 6-1 on page 7 shows the block diagram of the AVR CPU architecture.  
Figure 6-1. Block Diagram of the AVR CPU architecture  
In order to maximize performance and parallelism, the AVR uses a Harvard architecture with  
separate memories and buses for program and data. Instructions in the program memory are  
executed with a single level pipelining. While one instruction is being executed, the next instruc-  
7
8386A–AVR–07/11  

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