6. Pinout
6.1
Pin Description
In the Pin Description table below:
• Identical sharing number indicates multifunction pins.
• Pd indicates a pin with built-in pull-down resistor.
• Pu indicates a pin with built-in pull-up resistor.
Table 6-1.
Pinout by Pin Name
Sharin
g
Pin Name
Pin Number
Type
Description
4, 13, 19, 25, 36, 43,
48, 57
GND
PWR
–
Digital ground. All of these pins should be returned to a ground plane.
Core power. All of these pins should be returned to nominal 1.8V or to
PWROUT if the built-in power switch is used.
VC18
12, 31, 46, 63
PWR
PWR
PWR
–
–
–
VC33
3, 32
18
Periphery power. All these pins should be returned to nominal 3.3V.
Power switch input; should be returned to nominal 1.8V even if the
power switch is not used.
PWRIN
Power switch output; should be connected to all VC18 pins if the power
switch is used
PWROUT
D7 - D0
17
PWR
I/O
–
1
Slave 8-bit interface data. Output if CS and RD are low (read from chip),
input if CS and WR are low (write to chip). Type of data defined by A0
input.
59, 58, 56, 55, 52,
51, 50, 49
59, 58, 56, 55, 52,
51, 50, 49
I/O7 - I/O0
P0.7 - P0.0
I/O
I/O
1
1
SmartMedia data or other peripheral data
59, 58, 56, 55, 52,
51, 50, 49
General-purpose I/O; can be programmed individually as input or
output.
Optional bit clocks for digital audio input. Used for sampling rate
conversion for external incoming digital audio such as AES/BEU or
S/Pdif.
CLAD3 - 0
59, 58, 56, 55
In
1
Optional word selects for digital audio input. Used for sampling rate
conversion for external incoming digital audio such as AES/BEU or
S/Pdif.
WSAD3 - 0
A0
52, 51, 50, 49
60
In
In
1
2
Slave 8-bit interface address. Indicates data/status or data/ctrl transfer
type (CS/RD, low or CS/WR low)
SMPD
P0.10
SCLK
CS
60
60
60
64
64
64
In
In
In
In
In
In
2
2
2
3
3
3
SmartMedia presence detect
General-purpose input pin
Serial slave synchronous interface input clock
Slave 8-bit interface chip select, active low.
General-purpose input pin
P0.11
SYNC
Serial slave synchronous interface input sync signal
Slave 8-bit interface write, active low. D7 - D0 data is sampled by chip
on WR rising edge if CS is low
WR
1
In
4
6
ATSAM3108B
6092C–DRMSD–12-Feb-07