ATSAM3108B

更新时间： 2024-01-20 16:29:28

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ATSAM3108B 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LFQFP,	针数：	64
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.84	Is Samacsys：	N
商用集成电路类型：	CONSUMER CIRCUIT	JESD-30 代码：	S-PQFP-G64
长度：	10 mm	功能数量：	1
端子数量：	64	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	1.95 V
最小供电电压 (Vsup)：	1.65 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	10 mm	Base Number Matches：	1

11. Reset and Power-down

During power up, the RESET input should be held low until the crystal oscillator and PLL are sta-

bilized, which takes max. 10 ms.

After the low to high transition of RESET, the following happens:

• All P24s enter an idle state.

• P16 program execution starts in built-in ROM.

The power-up sequence is as follows:

• STIN is sensed. If HIGH, then the built-in debugger is started.

• SMC is sensed. If LOW, then the built-in loader waits for SmartMedia presence detect

(SMPD). When detected, the firmware is down loaded from SmartMedia reserved sector 1

and started.

• An attempt is made to read the first two bytes of an external EEPROM or DataFlash. If "DR"

is read, then the built-in loader loads the firmware from the external EEPROM/DataFlash and

starts it.

• Firmware download from a host processor is assumed.

1. The 0ACh byte is written to the host, this raises IRQ. The host can recognize that the

chip is ready to accept program download. Higher speed transfer can be reached by

polling the parallel interface status (CS = 0, A0 = 1, RD = 0).

2. The host sends the firmware size (in words) on two bytes (Low byte first).

3. The host sends the ATSAM3108B firmware. The firmware should begin with string

"DR".

4. The 0ACh byte is written to the host, this raises IRQ. The host can recognize that the

chip has accepted the firmware.

5. ATSAM3108B starts the firmware.

If PDWN is asserted low, then the crystal oscillator and PLL will be stopped. If the power switch

is used, then the chip enters a deep power down sleep mode, as power is removed from the

core. To exit power down, PDWN has to be asserted high, then RESET applied.

Other power reduction features allowing warm restart are controlled by firmware:

• P24s can be individually stopped.

• The clock frequency can be internally divided by 256.

ATSAM3108B

6092C–DRMSD–12-Feb-07

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