Datasheet > ATR0630-EK1

ATR0630-EK1

更新时间： 2024-01-30 17:29:38

品牌	Logo	应用领域
爱特美尔 - ATMEL		全球定位系统
页数	文件大小	规格书
14页	321K
描述
ANTARIS4 Single-chip GPS Receiver

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ATR0630-EK1 数据手册

ATR0630P1

2.7

2.8

VGA/AGC

The on-chip automatic gain control (AGC) stage sets the gain of the VGA in order to optimally

load the input of the following analog-to-digital converter. The AGC control loop can be selected

for on-chip closed-loop operation or for baseband controlled gain mode.

Analog-to-digital Converter

The analog-to-digital converter stage has a total resolution of 1.5 bits. It comprises balanced

comparators and a sub-sampling unit, clocked by the reference frequency (f_XTO). The frequency

spectrum of the digital output signal (f_OUT), present at the data outputs SIGLO and SIGH1, is

4.348 MHz.

2.9

Baseband

The GPS baseband core includes a 16-channel correlator and is based on an ARM7TDMI ARM

processor core with very low power consumption. It has a high-performance 32 bit RISC archi-

tecture, uses a high-density 16-bit instruction set, The ARM standard In-Circuit Emulation debug

interface is supported via the JTAG/ICE port of the ATR0630P1.

The ATR0630P1 architecture consists of two main buses, the Advanced System Bus (ASB) and

the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It inter-

faces the processor with the on-chip 32-bit memories and the external memories and devices by

means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip periph-

erals and is optimized for low power consumption. The AMBA^™Bridge provides an interface

between the ASB and the APB.

An on-chip Peripheral Data Controller (PDC2) transfers data between the on-chip USARTs/SPI

and the on- and off-chip memories without processor intervention. Most importantly, the PDC2

removes the processor interrupt handling overhead and significantly reduces the number of

clock cycles required for a data transfer. It can transfer up to 64K contiguous bytes without

reprogramming the starting address. As a result, the performance of the microcontroller is

increased and the power consumption reduced.

All of the external signals of the on-chip peripherals are under the control of the Parallel I/O Con-

troller (PIO2). The PIO2 Controller can be programmed to insert an input filter on each pin or

generate an interrupt on a signal change. After reset, the user must carefully program the PIO2

Controller in order to define which peripheral signals are connected with off-chip logic.

The ATR0630P1 features a Programmable Watchdog Timer.

An Advanced Power Management Controller (APMC) allows for the peripherals to be deacti-

vated individually. Automatic master clock gearing reduces power consumption. A Sleep Mode

is available with disabled 23.104 MHz master clock, as well as a Back-up Mode operating

32.768 kHz master clock.

A 32.768 kHz Real Time Clock (RTC), together with a buit-in battery back-up SRAM, allows for

storage of Almanac, Ephemeris, software configurations to make quick hot- and warm starts.

The ATR0630P1 includes full GPS firmware, licensed from u-blox AG, Switzerland. Features of

the ROM firmware are described in software documentation available from u-blox AG,

Switzerland.

4978AS–GPS–12/07

1 2 3 456 7 8...14

中文翻译

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与ATR0630-EK1相关器件

型号	品牌	获取价格	描述	数据表
ATR0630P1	ATMEL	获取价格	ANTARIS4 Single-chip GPS Receiver
ATR0630P1-7KQY	ATMEL	获取价格	ANTARIS4 Single-chip GPS Receiver
ATR0635	ATMEL	获取价格	ANTARIS4 Single-chip GPS Receiver SuperSense
ATR0635_08	ATMEL	获取价格	ANTARIS4 Single-chip GPS Receiver SuperSense
ATR0635-7KQY	ATMEL	获取价格	ANTARIS4 Single-chip GPS Receiver SuperSense
ATR0635-DK1	ATMEL	获取价格	ANTARIS4 Single-chip GPS Receiver SuperSense
ATR0635-EK1	ATMEL	获取价格	ANTARIS4 Single-chip GPS Receiver SuperSense
ATR0635P1	ATMEL	获取价格	ANTARIS4 Single-chip GPS Receiver SuperSense
ATR0635P1-7KQY	ATMEL	获取价格	ANTARIS4 Single-chip GPS Receiver SuperSense
ATR0640	ATMEL	获取价格	Telecom Circuit, 1-Func, CMOS, PBGA160, 12 X 12 MM, 0.80 MM PITCH, LFBGA-160

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