Datasheet > 可编程逻辑 > 可编程逻辑器件> ATF22LV10CQZ-30XC

ATF22LV10CQZ-30XC

更新时间： 2024-02-23 22:48:45

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
19页	347K
描述
Highperformance EE PLD

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技术参数
数据手册

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ATF22LV10CQZ-30XC 技术参数

生命周期：	Active	包装说明：	TSSOP,
Reach Compliance Code：	compliant	风险等级：	5.67
最大时钟频率：	25 MHz	JESD-30 代码：	R-PDSO-G24
长度：	7.8 mm	专用输入次数：	11
I/O 线路数量：	10	端子数量：	24
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	11 DEDICATED INPUTS, 10 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
可编程逻辑类型：	FLASH PLD	传播延迟：	30 ns
座面最大高度：	1.2 mm	最大供电电压：	5.5 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
宽度：	4.4 mm	Base Number Matches：	1

ATF22LV10CQZ-30XC 数据手册

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4.4

Input Test Waveforms

4.4.1

Input Test Waveforms and Measurement Levels

4.4.2

Output Test Loads

Note:

Similar competitors devices are specified with slightly different loads. These load differences may

affect output signals’ delay and slew rate. Atmel devices are tested with sufficient margins to meet

compatible device specification conditions.

4.5

4.6

Pin Capacitance

Table 4-1.

Pin Capacitance (f = 1 MHz, T = 25°C⁽¹⁾)

Typ

Max

Units

Conditions

V_IN= 0V

C_IN

C_I/O

V_OUT= 0V

Note:

1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100%

tested.

Power-up Reset

The registers in the ATF22LV10CZ/CQZ are designed to reset during power-up. At a point

delayed slightly from V_CCcrossing V_RST, all registers will be reset to the low state. The output

state will depend on the polarity of the buffer.

This feature is critical for state machine initialization. However, due to the asynchronous nature

of reset and the uncertainty of how V_CCactually rises in the system, the following conditions are

required:

1. The V_CCrise must be monotonic and start below 0.7V.

2. The clock must remain stable during T_PR

3. After T_PR, all input and feedback setup times must be met before driving the clock pin

high.

4.7

Preload of Register Outputs

The ATF22LV10CZ/CQZ’s registers are provided with circuitry to allow loading of each register

with either a high or a low. This feature will simplify testing since any state can be forced into the

registers to control test sequencing. A JEDEC file with preload is generated when a source file

ATF22LV10C(Q)Z

0779L–PLD–12/05

1...3 4 567 8 9...19

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