Datasheet > 可编程逻辑 > 可编程逻辑器件> ATF22LV10CQZ-30SU

ATF22LV10CQZ-30SU

更新时间： 2024-01-23 04:28:13

品牌	Logo	应用领域
爱特美尔 - ATMEL		可编程逻辑光电二极管输入元件时钟
页数	文件大小	规格书
19页	347K
描述
Highperformance EE PLD

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技术参数
数据手册

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ATF22LV10CQZ-30SU 技术参数

生命周期：	Active	包装说明：	TSSOP,
Reach Compliance Code：	compliant	风险等级：	5.67
最大时钟频率：	25 MHz	JESD-30 代码：	R-PDSO-G24
长度：	7.8 mm	专用输入次数：	11
I/O 线路数量：	10	端子数量：	24
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	11 DEDICATED INPUTS, 10 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
可编程逻辑类型：	FLASH PLD	传播延迟：	30 ns
座面最大高度：	1.2 mm	最大供电电压：	5.5 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
宽度：	4.4 mm	Base Number Matches：	1

ATF22LV10CQZ-30SU 数据手册

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ATF22LV10C(Q)Z

with vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done auto-

matically by most of the approved programmers after the programming.

5. Electronic Signature Word

There are 64 bits of programmable memory that are always available to the user, even if the

device is secured. These bits can be used for user-specific data.

6. Security Fuse Usage

A single fuse is provided to prevent unauthorized copying of the ATF22LV10CZ/CQZ fuse pat-

terns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User

Signature remains accessible.

The security fuse should be programmed last, as its effect is immediate.

7. Programming/Erasing

Programming/erasing is performed using standard PLD programmers. See CMOS PLD Pro-

gramming Hardware & Software Support for information on software/ programming.

Table 7-1.

Parameter

Programming/Erasing

Description

Typ

Max

Units

Power-up

Reset Time

T_PR

600

1000

Power-up

Reset Voltage

V_RST

2.3

2.7

8. Input and I/O Pin Keepers

All ATF22LV10CZ/CQZ family members have internal input and I/O pin-keeper circuits. There-

fore, whenever inputs or I/Os are not being driven externally, they will maintain their last driven

state. This ensures that all logic array inputs and device outputs are at known states. These are

relatively weak active circuits that can be easily overridden by TTL-compatible drivers (see input

and I/O diagrams below).

Figure 8-1. Input Diagram

V_CC

100K

INPUT

ESD

PROTECTION

CIRCUIT

0779L–PLD–12/05

1...4 5 678 9 10...19

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