Datasheet > ATF20V8B_06

ATF20V8B_06

更新时间： 2022-12-27 23:41:19

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
22页	656K
描述
Highperformance EE PLD

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数据手册

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ATF20V8B_06 数据手册

ATF20V8B(Q)(L)

Input Test Waveforms and

Measurement Levels

Output Test Loads

Commercial

t_R, t_F< 5 ns (10% to 90%)

Pin Capacitance

f = 1 MHz, T = 25°C⁽¹⁾

Typ

Max

Units

Conditions

V_IN= 0V

C_IN

C_OUT

Note:

V_OUT= 0V

1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.

Power-up Reset

The registers in the ATF20V8Bs are designed to reset dur-

ing power-up. At a point delayed slightly from V_CCcrossing

_RST, all registers will be reset to the low state. As a result,

the registered output state will always be high on power-up.

This feature is critical for state machine initialization. How-

ever, due to the asynchronous nature of reset and the

uncertainty of how V_CCactually rises in the system, the fol-

lowing conditions are required:

1. The V_CCrise must be monotonic,

2. After reset occurs, all input and feedback setup

times must be met before driving the clock pin high,

and

Parameter Description

Typ

600 1,000

3.8 4.5

Max

Units

3. The clock must remain stable during t_PR

t_PR

Power-up Reset Time

Power-up Reset Voltage

V_RST

Preload of Registered Outputs

The ATF16V8B’s registers are provided with circuitry to

allow loading of each register with either a high or a low.

This feature will simplify testing since any state can be

forced into the registers to control test sequencing. A

JEDEC file with preload is generated when a source file

with vectors is compiled. Once downloaded, the JEDEC file

preload sequence will be done automatically by most of the

approved programmers after the programming.

Security Fuse Usage

A single fuse is provided to prevent unauthorized copying

of the ATF20V8B fuse patterns. Once programmed, fuse

verify and preload are inhibited. However, the 64-bit User

Signature remains accessible.

The security fuse should be programmed last, as its effect

is immediate.

Electronic Signature Word

There are 64 bits of programmable memory that are always

available to the user, even if the device is secured. These

bits can be used for user-specific data.

Programming/Erasing

Programming/erasing is performed using standard PLD

programmers. For further information, see the Configurable

Logic Databook, section titled, “CMOS PLD Programming

Hardware and Software Support.”

1 2 3 456 7 8...22

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