Datasheet > 可编程逻辑 > 可编程逻辑器件> ATF1508AS-7JX84

ATF1508AS-7JX84

更新时间： 2024-02-03 22:31:02

品牌	Logo	应用领域
爱特美尔 - ATMEL		可编程逻辑器件输入元件异步传输模式 PC ATM 时钟
页数	文件大小	规格书
31页	692K
描述
Highperformance EE PLD

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技术参数
数据手册

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ATF1508AS-7JX84 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	QCCJ, LDCC84,1.2SQ
Reach Compliance Code：	compliant	风险等级：	5.55
Samacsys Confidence：	4	Samacsys Status：	Released
Schematic Symbol：	https://componentsearchengine.com/symbol.php?partID=333688	PCB Footprint：	https://componentsearchengine.com/footprint.php?partID=333688
Samacsys PartID：	333688	Samacsys Image：	https://componentsearchengine.com/Images/9/ATF1508AS-7JX84.jpg
Samacsys Thumbnail Image：	https://componentsearchengine.com/Thumbnails/1/ATF1508AS-7JX84.jpg	Samacsys Pin Count：	84
Samacsys Part Category：	Integrated Circuit	Samacsys Package Category：	Plastic Leaded Chip Carrier
Samacsys Footprint Name：	(L)84-Lead(PLCC)-1	Samacsys Released Date：	2019-07-24 13:44:07
Is Samacsys：	N	其他特性：	YES
最大时钟频率：	166.7 MHz	系统内可编程：	YES
JESD-30 代码：	S-PQCC-J84	JESD-609代码：	e3
JTAG BST：	YES	长度：	29.3115 mm
湿度敏感等级：	2	专用输入次数：
I/O 线路数量：	64	宏单元数：	128
端子数量：	84	最高工作温度：	70 °C
最低工作温度：		组织：	0 DEDICATED INPUTS, 64 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC84,1.2SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	245	电源：	3.3/5,5 V
可编程逻辑类型：	EE PLD	传播延迟：	7.5 ns
认证状态：	Not Qualified	座面最大高度：	4.572 mm
子类别：	Programmable Logic Devices	最大供电电压：	5.25 V
最小供电电压：	4.75 V	标称供电电压：	5 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子面层：	MATTE TIN	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	29.3115 mm
Base Number Matches：	1

ATF1508AS-7JX84 数据手册

ATF1508AS(L)

Speed/Power

Management

The ATF1508AS has several built-in speed and power management features. The

ATF1508AS contains circuitry that automatically puts the device into a low-power stand-by

mode when no logic transitions are occurring. This not only reduces power consumption dur-

ing inactive periods, but also provides proportional power-savings for most applications

running at system speeds below 5 MHz.

To further reduce power, each ATF1508AS macrocell has a Reduced-power bit feature. This

feature allows individual macrocells to be configured for maximum power savings. This feature

may be selected as a design option.

I/O Diagram

All ATF1508 also have an optional power-down mode. In this mode, current drops to below 10

mA. When the power-down option is selected, either PD1 or PD2 pins (or both) can be used to

power down the part. The power-down option is selected in the design source file. When

enabled, the device goes into power-down when either PD1 or PD2 is high. In the power-down

mode, all internal logic signals are latched and held, as are any enabled outputs.

All pin transitions are ignored until the PD pin is brought low. When the power-down feature is

enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s

macrocell may still be used to generate buried foldback and cascade logic signals.

All power-down AC characteristic parameters are computed from external input or I/O pins,

with Reduced-power Bit turned on. For macrocells in reduced-power mode (Reduced-power

bit turned on), the reduced-power adder, tRPA, must be added to the AC parameters, which

include the data paths t_LAD, t_LAC, t_IC, t_ACL, t_ACHand t_SEXP

Each output also has individual slew rate control. This may be used to reduce system noise by

slowing down outputs that do not need to operate at maximum speed. Outputs default to slow

switching, and may be specified as fast switching in the design file.

0784P–PLD–7/05

1...4 5 678 9 10...31

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