Datasheet > ATF1508ASV

ATF1508ASV

更新时间： 2022-12-13 16:03:17

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
22页	500K
描述
Highperformance EE PLD

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数据手册

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ATF1508ASV 数据手册

Features

• High-density, High-performance, Electrically-erasable

Complex Programmable Logic Device

– 3.0V to 3.6V Operating Range

– 128 Macrocells

– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

– 84, 100, 160 Pins

– 15 ns Maximum Pin-to-pin Delay

– Registered Operation up to 77 MHz

– Enhanced Routing Resources

• Flexible Logic Macrocell

High-

performance

EE PLD

– D/T/Latch Configurable Flip-flops

– Global and Individual Register Control Signals

– Global and Individual Output Enable

– Programmable Output Slew Rate

– Programmable Output Open Collector Option

– Maximum Logic Utilization by Burying a Register within a COM Output

• Advanced Power Management Features

– Automatic 5 µA Standby for “L” Version

– Pin-controlled 100 µA Standby Mode

– Programmable Pin-keeper Inputs and I/Os

– Reduced-power Feature per Macrocell

• Available in Commercial and Industrial Temperature Ranges

• Available in 84-lead PLCC and 100-lead PQFP and TQFP and

160-lead PQFP Packages

ATF1508ASV

ATF1508ASVL

• Advanced EE Technology

– 100% Tested

– Completely Reprogrammable

– 10,000 Program/Erase Cycles

– 20 Year Data Retention

– 2000V ESD Protection

– 200 mA Latch-up Immunity

• JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

• Fast In-System Programmability (ISP) via JTAG

• PCI-compliant

• Security Fuse Feature

Enhanced Features

• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

• Output Enable Product Terms

• Transparent-latch Mode

• Combinatorial Output with Registered Feedback within Any Macrocell

• Three Global Clock Pins

• ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O

• Fast Registered Input from Product Term

• Programmable “Pin-keeper” Option

• V_CCPower-up Reset Option

• Pull-up Option on JTAG Pins TMS and TDI

• Advanced Power Management Features

– Edge-controlled Power-down “L”

– Individual Macrocell Power Option

– Disable ITD on Global Clocks, Inputs and I/O for “Z” Parts

Rev. 1408E–09/00

12 3 4 5 6 7...22

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