Datasheet > 可编程逻辑 > 可编程逻辑器件> ATF1508AS-7JX84

ATF1508AS-7JX84

更新时间： 2024-02-07 09:54:00

品牌	Logo	应用领域
爱特美尔 - ATMEL		可编程逻辑器件输入元件异步传输模式 PC ATM 时钟
页数	文件大小	规格书
31页	692K
描述
Highperformance EE PLD

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技术参数
数据手册

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ATF1508AS-7JX84 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	QCCJ, LDCC84,1.2SQ
Reach Compliance Code：	compliant	风险等级：	5.55
Samacsys Confidence：	4	Samacsys Status：	Released
Schematic Symbol：	https://componentsearchengine.com/symbol.php?partID=333688	PCB Footprint：	https://componentsearchengine.com/footprint.php?partID=333688
Samacsys PartID：	333688	Samacsys Image：	https://componentsearchengine.com/Images/9/ATF1508AS-7JX84.jpg
Samacsys Thumbnail Image：	https://componentsearchengine.com/Thumbnails/1/ATF1508AS-7JX84.jpg	Samacsys Pin Count：	84
Samacsys Part Category：	Integrated Circuit	Samacsys Package Category：	Plastic Leaded Chip Carrier
Samacsys Footprint Name：	(L)84-Lead(PLCC)-1	Samacsys Released Date：	2019-07-24 13:44:07
Is Samacsys：	N	其他特性：	YES
最大时钟频率：	166.7 MHz	系统内可编程：	YES
JESD-30 代码：	S-PQCC-J84	JESD-609代码：	e3
JTAG BST：	YES	长度：	29.3115 mm
湿度敏感等级：	2	专用输入次数：
I/O 线路数量：	64	宏单元数：	128
端子数量：	84	最高工作温度：	70 °C
最低工作温度：		组织：	0 DEDICATED INPUTS, 64 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC84,1.2SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	245	电源：	3.3/5,5 V
可编程逻辑类型：	EE PLD	传播延迟：	7.5 ns
认证状态：	Not Qualified	座面最大高度：	4.572 mm
子类别：	Programmable Logic Devices	最大供电电压：	5.25 V
最小供电电压：	4.75 V	标称供电电压：	5 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子面层：	MATTE TIN	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	29.3115 mm
Base Number Matches：	1

ATF1508AS-7JX84 数据手册

ATF1508AS(L)

Flip-flop

The ATF1508AS’s flip-flop has very flexible data and control functions. The data input can

come from either the XOR gate, from a separate product term or directly from the I/O pin.

Selecting the separate product term allows creation of a buried registered feedback within a

combinatorial output macrocell. (This feature is automatically implemented by the fitter soft-

ware). In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flow-

through latch. In this mode, data passes through when the clock is high and is latched when

the clock is low.

The clock itself can be either the Global CLK Signal (GCK) or an individual product term. The

flip-flop changes state on the clock’s rising edge. When the GCK signal is used as the clock,

one of the macrocell product terms can be selected as a clock enable. When the clock enable

function is active and the enable signal (product term) is low, all clock edges are ignored. The

flip-flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product

term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchro-

nous preset (AP) can be a product term or always off.

Extra Feedback

I/O Control

The ATF15xxSE Family macrocell output can be selected as registered or combinatorial. The

extra buried feedback signal can be either combinatorial or a registered signal regardless of

whether the output is combinatorial or registered. (This enhancement function is automatically

implemented by the fitter software.) Feedback of a buried combinatorial output allows the cre-

ation of a second latch within a macrocell.

The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be indi-

vidually configured as an input, output or for bi-directional operation. The output enable for

each macrocell can be selected from the true or compliment of the two output enable pins, a

subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done

by the fitter software when the I/O is configured as an input, all macrocell resources are still

available, including the buried feedback, expander and cascade logic.

Global Bus/Switch

Matrix

The global bus contains all input and I/O pin signals as well as the buried feedback signal from

all 128 macrocells. The switch matrix in each logic block receives as its inputs all signals from

the global bus. Under software control, up to 40 of these signals can be selected as inputs to

the logic block.

Foldback Bus

Each macrocell also generates a foldback product term. This signal goes to the regional bus

and is available to 16 macrocells. The foldback is an inverse polarity of one of the macrocell’s

product terms. The 16 foldback terms in each region allows generation of high fan-in sum

terms (up to 21 product terms) with a little additional delay.

3.3V or 5.0V I/O

Operation

The ATF1508AS device has two sets of V_CCpins viz, V_CCINTand V_CCIO. V_CCINTpins must

always be connected to a 5.0V power supply. V_CCINTpins are for input buffers and are “com-

patible” with both 3.3V and 5.0V inputs. V_CCIOpins are for I/O output drives and can be

connected for 3.3/5.0V power supply.

Open-collector

Output Option

This option enables the device output to provide control signals such as an interrupt that can

be asserted by any of the several devices.

0784P–PLD–7/05

1 2 3 456 7 8...31

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ATF1508AS-7QL100	ATMEL	EE PLD, 7.5ns, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100	获取价格
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