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ATF1504SE-5JC84 PDF预览

ATF1504SE-5JC84

更新时间: 2022-12-01 19:40:29
品牌 Logo 应用领域
爱特美尔 - ATMEL /
页数 文件大小 规格书
69页 601K
描述
EE PLD, 5ns, 64-Cell, CMOS, PQCC84, PLASTIC, LCC-84

ATF1504SE-5JC84 数据手册

 浏览型号ATF1504SE-5JC84的Datasheet PDF文件第2页浏览型号ATF1504SE-5JC84的Datasheet PDF文件第3页浏览型号ATF1504SE-5JC84的Datasheet PDF文件第4页浏览型号ATF1504SE-5JC84的Datasheet PDF文件第6页浏览型号ATF1504SE-5JC84的Datasheet PDF文件第7页浏览型号ATF1504SE-5JC84的Datasheet PDF文件第8页 
ATF15xxSE Family  
Figure 2. ATF15xxSE Family Macrocell with Enhanced Features In Red  
Product Terms and  
Select Mux  
Within each macrocell are five product terms. Each product term may receive as its inputs any  
combination of the signals from the switch matrix or regional foldback bus. The product term  
select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic  
gates and control signals. The PTMUX programming is determined by the fitter software,  
which selects the optimum macrocell configuration.  
OR/XOR/  
CASCADE Logic  
Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5-  
input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can  
be expanded to as many as 40 product terms with little additional delay.  
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic func-  
tions. One input to the XOR comes from the OR sum term. The other XOR input can be a  
product term or a fixed high- or low-level. For combinatorial outputs, the fixed level input  
allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimiza-  
tion of product terms. The XOR gate may be fed from the flip-flop output to emulate T- and JK-  
type flip-flops, or fed to the buried feedback to synthesize an extra latch.  
Foldback Bus  
Each macrocell can also generate a foldback product term. This signal goes to the regional  
bus and is available to the 16 macrocells in a given logic block. The foldback is an inverse  
polarity of one of the macrocell’s product terms. Although Cascade Logic is the preferred  
method for expanding the number of macrocell inputs to as many as 40, the 16 foldback terms  
in each region can also generate additional fan-in sum terms with nominal additional delay.  
5
2401D–PLD–09/02  

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