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ATF1504ASVL PDF预览

ATF1504ASVL

更新时间: 2023-12-06 20:08:50
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
30页 847K
描述
Low Power, Vcc-3.3V, 64 MC, ISP, Green package, CPLD

ATF1504ASVL 数据手册

 浏览型号ATF1504ASVL的Datasheet PDF文件第4页浏览型号ATF1504ASVL的Datasheet PDF文件第5页浏览型号ATF1504ASVL的Datasheet PDF文件第6页浏览型号ATF1504ASVL的Datasheet PDF文件第8页浏览型号ATF1504ASVL的Datasheet PDF文件第9页浏览型号ATF1504ASVL的Datasheet PDF文件第10页 
ATF1504ASV/ATF1504ASVL  
All power-down AC characteristic parameters are com-  
When the Large hysteresis option is active, ICC is  
reduced by several hundred microamps as well.  
puted from external input or I/O pins, with  
reduced-power bit turned on. For macrocells in  
Reduced-Power mode (reduced-power bit turned on),  
the reduced-power adder, tRPA, must be added to the  
AC parameters, which include the data paths tLAD,  
tLAC, tIC, tACL or tACH, tEN and tSEXP.  
Details on the power Reset hysteresis feature are avail-  
able in the “ATF15XX Power-on Reset Hysteresis Fea-  
ture” application note.  
Security Fuse Usage  
The ATF1504ASV(L) macrocell also has an option  
whereby the power can be reduced on a per macrocell  
basis. By enabling this power-down option, macrocells  
that are not used in an application can be turned down,  
thereby reducing the overall power consumption of the  
device. This option is automatically set by the device  
fitter software.  
A single fuse is provided to prevent unauthorized copy-  
ing of the ATF1504ASV(L) fuse patterns. Once pro-  
grammed, fuse verify is inhibited. However, the 16-bit  
User Signature remains accessible.  
Programming  
Each output also has individual slew rate control. This  
may be used to reduce system noise by slowing down  
outputs that do not need to operate at maximum speed.  
Outputs default to slow switching, and may be specified  
as fast switching in the design software or design file.  
ATF1504ASV(L) devices are in-system programmable  
(ISP) devices utilizing the 4-pin JTAG protocol. This  
capability eliminates package handling normally  
required for programming and facilitates rapid design  
iterations and field changes.  
Microchip provides ISP hardware and software to allow  
programming of the ATF1504ASV(L) via the PC. ISP is  
performed by using either a download cable, a compa-  
rable board tester or a simple microprocessor interface.  
Design Software Support  
ATF1504ASV(L) designs are supported by Microchip’s  
ProChip Designer and WinCUPL software tools as well  
as Precision Synthesis from Mentor Graphic as  
described in the “Programmable Logic Device Design  
Software Overview”.  
To facilitate ISP programming by the Automated Test  
Equipment (ATE) vendors, Serial Vector Format (SVF)  
files can be created by Microchip provided software  
utilities.  
Power-Up Reset  
ATF1504ASV(L) devices can also be programmed  
using standard third-party programmers. With  
a
The ATF1504ASV/ATF1504ASVL is designed with a  
power-up Reset, a feature critical for state machine ini-  
tialization. At a point delayed slightly from VCC crossing  
VRST, all registers will be initialized, and the state of  
each output will depend on the polarity of its buffer.  
However, due to the asynchronous nature of Reset and  
uncertainty of how VCC actually rises in the system, the  
following conditions are required:  
third-party programmer, the JTAG ISP port can be dis-  
abled, thereby allowing four additional I/O pins to be  
used for logic.  
Refer to Programming of PLDs application note for  
more details.  
ISP Programming Protection  
• The VCC rise must be monotonic  
The ATF1504ASV(L) has a special feature that locks  
the device and prevents the inputs and I/O from driving  
if the programming process is interrupted for any rea-  
son. The inputs and I/O default to high Z state during  
such a condition. In addition, the pin-keeper option pre-  
serves the former state during device programming, if  
this circuit was previously programmed on the device.  
This prevents disturbing the operation of other circuits  
in the system while the ATF1504ASV(L) is being pro-  
grammed via ISP.  
• After Reset occurs, all input and feedback setup  
times must be met before driving the clock pin  
high  
• The clock must remain stable during Power-up  
Reset  
The ATF1504ASV/ATF1504ASVL has two options for  
the hysteresis about the Reset level, VRST, Small and  
Large. To ensure a robust operating environment in  
applications where the device is operated near 3.0V, it  
is recommended that during the fitting process users  
configure the device with the Power-up Reset hystere-  
sis set to Large. Users of the POF2JED conversion util-  
ity should include the flag “-power_reset” on the  
command line after “filename.POF”. To allow the regis-  
ters to be properly reinitialized with the Large hystere-  
sis option selected, the following condition is added:  
All ATF1504ASV(L) devices are initially shipped in the  
erased state, thereby making them ready to use for ISP.  
• If VCC falls below 2.0V, it must shut off completely  
before the device is turned on again  
2019 Microchip Technology Inc.  
DS20006185A-page 7  

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