Datasheet > 可编程逻辑 > 可编程逻辑器件> ATF1502AS-7QC44

ATF1502AS-7QC44

更新时间： 2024-02-05 02:38:16

品牌	Logo	应用领域
爱特美尔 - ATMEL		可编程逻辑器件输入元件异步传输模式 ATM 可编程只读存储器时钟
页数	文件大小	规格书
18页	347K
描述
High Performance E2PROM CPLD

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技术参数
数据手册

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ATF1502AS-7QC44 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	QFP, QFP44,.5SQ,32
针数：	44	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.8
其他特性：	YES	最大时钟频率：	166.7 MHz
系统内可编程：	YES	JESD-30 代码：	S-PQFP-G44
JESD-609代码：	e0	JTAG BST：	YES
长度：	10 mm	专用输入次数：
I/O 线路数量：	32	宏单元数：	32
端子数量：	44	最高工作温度：	70 °C
最低工作温度：		组织：	0 DEDICATED INPUTS, 32 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP44,.5SQ,32
封装形状：	SQUARE	封装形式：	FLATPACK
峰值回流温度（摄氏度）：	240	电源：	3.3,5 V
可编程逻辑类型：	EE PLD	传播延迟：	7.5 ns
认证状态：	Not Qualified	座面最大高度：	2.45 mm
子类别：	Programmable Logic Devices	最大供电电压：	5.25 V
最小供电电压：	4.75 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	10 mm	Base Number Matches：	1

ATF1502AS-7QC44 数据手册

JTAG-BST/ISP Overview

BSC Configuration for Input and I/O

Pins (except JTAG TAP Pins)

The JTAG boundary-scan testing is controlled by the Test

Access Port (TAP) controller in the ATF1502AS. The

boundary-scan technique involves the inclusion of a shift-

to each component so that signals at component bound-

aries can be controlled and observed using scan testing

methods. Each input pin and I/O pin has its own boundary

scan cell (BSC) to support boundary scan testing. The

ATF1502AS does not include a Test Reset (TRST) input

pin because the TAP controller is automatically reset at

power up. The five JTAG modes supported include: SAM-

PLE/PRELOAD, EXTEST, BYPASS, IDCODE and HIGHZ.

The ATF1502AS’s ISP can be fully described using JTAG’s

BSDL as described in IEEE Standard 1149.1b. This allows

ATF1502AS programming to be described and imple-

mented using any one of the 3rd party development tools

supporting this standard.

Note:

The ATF1502AS has pull-up option on TMS and TDI

pins. This feature is selected as a design option.

The ATF1502AS has the option of using four JTAG-stan-

dard I/O pins for boundary scan testing (BST) and in-sys-

tem programming (ISP) purposes. The ATF1502AS is

programmable through the four JTAG pins using the IEEE

standard JTAG programming protocol established by IEEE

Standard 1149.1 using 5V TTL-level programming signals

from the ISP interface for in-system programming. The

JTAG feature is a programmable option. If JTAG (BST or

ISP) is not needed, then the four JTAG control pins are

available as I/O pins.

DC and AC Operating Conditions

Commercial

Industrial

Operating Temperature (Case)

_CCINTor V_CCIO(5V) Power

0°C - 70°C

-40°C - 85°C

5V ± 10%

5V ± 5%

Supply

V_CCIO(3.3V) Power Supply

3.0V - 3.6V

JTAG Boundary Scan Cell (BSC)

Testing

The ATF1502AS contains up to 32 I/O pins and 4 input

pins, depending on the and package type selected. Each

input pin and I/O pin has its own boundary scan cell (BSC)

in order to support boundary scan testing as described in

detail by IEEE Standard 1149.1. Typical BSC consists of

three capture registers or scan registers and up to two

update registers. There are two types of BSCs, one for

input or I/O pin, and one for the macrocells. The BSCs in

the device are chained together through the capture regis-

ters. Input to the capture register chain is fed in from the

TDI pin while the output is directed to the TDO pin. Capture

registers are used to capture active device data signals, to

shift data in and out of the device and to load data into the

update registers. Control signals are generated internally

by the JTAG TAP controller. The BSC configuration for the

input and I/O pins and macrocells are shown below.

ATF1502AS

1...3 4 567 8 9...18

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