ATF1502AS
option is selected in the design source file. When enabled,
the device goes into power down when either PD1 or PD2
is high. In the power down mode, all internal logic signals
are latched and held, as are any enabled outputs.
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup
times must be met before driving the clock pin-
high, and,
All pin transitions are ignored until the PD pin is brought
low. When the power down feature is enabled, the PD1 or
PD2 pin cannot be used as a logic input or output. How-
ever, the pin’s macrocell may still be used to generate bur-
ied foldback and cascade logic signals.
3. The clock must remain stable during TD.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF1502AS fuse patterns. Once programmed, fuse
verify is inhibited. However, the 16-bit User Signature
remains accessible.
All Power-Down AC Characteristic parameters are com-
puted from external input or I/O pins, with Reduced Power
Bit turned on. For macrocells in reduced-power mode
(Reduced power bit turned on), the reduced power adder,
tRPA, must be added to the AC parameters, which include
Programming
the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP
.
ATF1502AS devices are In-System Programmable (ISP)
devices utilizing the 4-pin JTAG protocol. This capability
eliminates package handling normally required for program
and facilitates rapid design iterations and field changes.
The ATF1502AS macrocell also has an option whereby the
power can be reduced on a per macrocell basis. By
enabling this power down option, macrocells that are not
used in an application can be turned down thereby reduc-
ing the overall power consumption of the device.
Atmel provides ISP hardware and software to allow pro-
gramming of the ATF1502AS via the PC. ISP is performed
by using either a download cable, or a comparable board
tester or a simple microprocessor interface.
Each output also has individual slew rate control. This may
be used to reduce system noise by slowing down outputs
that do not need to operate at maximum speed. Outputs
default to slow switching, and may be specified as fast
switching in the design file.
When using the ISP hardware or S/W to program the
ATF1502AS devices, four I/0 pins must be reserved for the
JTAG interface. However, the logic features the macrocells
associated with these I/0 pins are still available to the
design for burned logic functions.
Design Software Support
ATF1502AS designs are supported by several third party
tools. Automated fitters allow logic synthesis using a variety
of high level description languages and formats.
To facilitate ISP programming by the Automated Test
Equipment (ATE) vendors. Serial Vector Format (SVF) files
can be created by Atmel provided Software utilities.
ATF1502AS devices can also be programmed using stan-
dard 3rd party programmers. With 3rd party programmer
the JTAG ISP port can be disabled thereby allowing 4 addi-
tional I/O pins to be used for logic.
Power Up Reset
The ATF1502AS has a power-up reset option at two differ-
ent voltage trip levels when the device is being powered
down. Within the fitter, or during a conversion, if the
“power-reset” option is turned “on” (which is the default
option), the trip levels during power up or power down is at
2.8V. The user can change this default option from “on” to
“off” (within the fitter or specify it as a switch during conver-
sion). When this is done, the voltage trip level during
power-down changes from 2.8V to 0.7V. This is to ensure a
robust operating environment.
Contact your local Atmel representatives or Atmel PLD
applications for details.
ISP Programming Protection
The ATF1502AS has a special feature which locks the
device and prevents the inputs and I/O from driving if the
programming process is interrupted due to any reason. The
inputs and I/O default to high-Z state during such a condi-
tion. In addition, the pin keeper option preserves the previ-
ous state of the input and I/0 PMS during programming.
The registers in the ATF1502AS are designed to reset dur-
ing power up. At a point delayed slightly from VCC crossing
Vrst, all registers will be reset to the low state. The output
state will depend on the polarity of the buffer.
All ATF1502AS devices are initially shipped in the erased
state thereby making them ready to use for ISP.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the fol-
lowing conditions are required:
Note:
For more information refer to the “Designing for In-Sys-
tem Programmability with Atmel CPLDs” application
note.
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