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ATF1500AL-25AI PDF预览

ATF1500AL-25AI

更新时间： 2024-01-25 03:16:49
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程逻辑器件
页数 文件大小 规格书
16页 683K
描述
High Performance E2 PLD

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ATF1500AL-25AI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：LPCC包装说明：QCCJ, LDCC44,.7SQ
针数：44Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.82
Is Samacsys：N其他特性：NO
最大时钟频率：43 MHz系统内可编程：NO
JESD-30 代码：S-PQCC-J44JESD-609代码：e0
JTAG BST：NO长度：16.5862 mm
湿度敏感等级：2专用输入次数：
I/O 线路数量：32宏单元数：32
端子数量：44最高工作温度：85 °C
最低工作温度：-40 °C组织：0 DEDICATED INPUTS, 32 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC44,.7SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：225电源：5 V
可编程逻辑类型：FLASH PLD传播延迟：25 ns
认证状态：Not Qualified座面最大高度：4.57 mm
子类别：Programmable Logic Devices最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：16.5862 mmBase Number Matches：1

ATF1500AL-25AI 数据手册

 浏览型号ATF1500AL-25AI的Datasheet PDF文件第8页浏览型号ATF1500AL-25AI的Datasheet PDF文件第9页浏览型号ATF1500AL-25AI的Datasheet PDF文件第10页浏览型号ATF1500AL-25AI的Datasheet PDF文件第12页浏览型号ATF1500AL-25AI的Datasheet PDF文件第13页浏览型号ATF1500AL-25AI的Datasheet PDF文件第14页 
ATF1500A/AL  
Power Up Reset  
The ATF1500A's registers are designed to reset during  
power up. At a point delayed slightly from VCC crossing  
VRST, all registers will be reset to the low state. As a result,  
the registered output state will always be low on power-up.  
This feature is critical for state machine initialization. How-  
ever, due to the asynchronous nature of reset and the  
uncertainty of how VCC actually rises in the system, the fol-  
lowing conditions are required:  
1. The VCC rise must be monotonic, from below .7 volts,  
2. After reset occurs, all input and feedback setup times  
must be met before driving the clock signal high, and  
3. Signals from which clocks are derived must remain sta-  
Parameter  
Description  
Typ  
Max  
Units  
ble during tPR  
.
Power-Up  
Reset Time  
tPR  
2
10  
µs  
Power Down Mode  
Power-Up  
Reset  
Voltage  
The ATF1500A includes an optional pin controlled power  
down feature. When this mode is enabled, the PD pin acts  
as the power down pin. When the PD pin is high, the device  
supply current is reduced to less than 10 µA. During power  
down, all output data and internal logic states are latched  
and held. Therefore, all registered and combinatorial output  
data remain valid. Any outputs which were in a HI-Z state at  
the onset of power down will remain at HI-Z. During power  
down, all input signals except the power down pin are  
blocked. Input and I/O hold latches remain active to insure  
that pins do not float to indeterminate levels, further reduc-  
ing system power. The power down pin feature is enabled  
in the logic design file. Designs using the power down pin  
may not use the PD pin logic array input. However, all other  
PD pin macrocell resources may still be used, including the  
buried feedback and foldback product term array inputs.  
VRST  
3.8  
4.5  
V
Output Slew Rate Control  
Each ATF1500A macrocell contains a configuration bit for  
each I/O to control its output slew rate. This allows selected  
data paths to operate at maximum throughput while reduc-  
ing system noise from outputs that are not speed-critical.  
Outputs default to slow edges, and may be individually set  
to fast in the design file. Output transition times for outputs  
configured as “slow” have a tSSO delay adder.  
Security Fuse Usage  
A single fuse is provided to prevent unauthorized copying  
of the ATF1500A fuse patterns. Once programmed, fuse  
verify and preload are prohibited. However, the 160-bit  
User Signature remains accessible.  
Register Preload  
The ATF1500A's registers are provided with circuitry to  
allow loading of each register with either a high or a low.  
This feature will simplify testing since any state can be  
forced into the registers to control test sequencing. A  
JEDEC file with preload is generated when a source file  
with preload vectors is compiled. Once downloaded, the  
JEDEC file preload sequence will be done automatically  
when vectors are run by any approved programmers. The  
preload mode is enabled by raising an input pin to a high  
voltage level. Contact Atmel PLD Applications for PRE-  
LOAD pin assignments, timing and voltage requirements.  
The security fuse should be programmed last, as its effect  
is immediate.  
11  
1...891011121314...16

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