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ATF1500AL-20JU PDF预览

ATF1500AL-20JU

更新时间: 2024-02-29 14:38:28
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程逻辑器件输入元件异步传输模式PCATM
页数 文件大小 规格书
19页 596K
描述
Highperformance EPLD

ATF1500AL-20JU 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:LPCC包装说明:QCCJ, TQFP44,.47SQ,32
针数:44Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.31.00.01
Factory Lead Time:1 week风险等级:5.55
Is Samacsys:N其他特性:NO
系统内可编程:NOJESD-30 代码:S-PQCC-J44
JESD-609代码:e3JTAG BST:NO
长度:16.586 mm湿度敏感等级:2
专用输入次数:I/O 线路数量:32
宏单元数:32端子数量:44
最高工作温度:85 °C最低工作温度:-40 °C
组织:0 DEDICATED INPUTS, 32 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:TQFP44,.47SQ,32封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):245
电源:5 V可编程逻辑类型:FLASH PLD
传播延迟:20 ns认证状态:Not Qualified
座面最大高度:4.572 mm子类别:Programmable Logic Devices
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:16.586 mm
Base Number Matches:1

ATF1500AL-20JU 数据手册

 浏览型号ATF1500AL-20JU的Datasheet PDF文件第1页浏览型号ATF1500AL-20JU的Datasheet PDF文件第2页浏览型号ATF1500AL-20JU的Datasheet PDF文件第3页浏览型号ATF1500AL-20JU的Datasheet PDF文件第5页浏览型号ATF1500AL-20JU的Datasheet PDF文件第6页浏览型号ATF1500AL-20JU的Datasheet PDF文件第7页 
ATF1500A(L) Macrocell  
ATF1500A Macrocell  
The ATF1500A macrocell is flexible enough to support  
highly-complex logic functions operating at high speed. The  
macrocell consists of five sections: product terms and prod-  
uct term select multiplexer, OR/XOR/CASCADE logic, a  
flip-flop, output select and enable, and logic array inputs.  
routed to the OR gate, creating a five input AND/OR sum  
term. With the addition of the CASIN from neighboring  
macrocells, this can be expanded to as many as 40 product  
terms with little small additional delay.  
The macrocell’s XOR gate allows efficient implementation  
of compare and arithmetic functions. One input to the XOR  
comes from the OR sum term. The other XOR input can be  
a product term or a fixed high or low level. For combinato-  
rial outputs, the fixed level input allows output polarity  
selection. For registered functions, the fixed levels allow De  
Morgan minimization of the product terms. The XOR gate is  
also used to emulate T-type flip-flops.  
Product Terms and Select Mux  
Each ATF1500A macrocell has five product terms. Each  
product term receives as its inputs all signals from both the  
global bus and regional bus.  
The product term select multiplexer (PTMUX) allocates the  
five product terms as needed to the macrocell logic gates  
and control signals. The PTMUX programming is deter-  
mined by the design compiler that selects the optimum  
macrocell configuration.  
Flip-flop  
The ATF1500A’s flip-flop has very flexible data and control  
functions. The data input can come from either the XOR  
gate or from a separate product term. Selecting the sepa-  
rate product term allows creation of a buried registered  
feedback within a combinatorial output macrocell.  
OR/XOR/CASCADE Logic  
The ATF1500A macrocell’s OR/XOR/CASCADE logic  
structure is designed to efficiently support all types of logic.  
Within a single macrocell, all the product terms can be  
ATF1500A(L)  
4

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