Datasheet > 可编程逻辑 > 可编程逻辑器件> ATF1500AL-20JU

ATF1500AL-20JU

更新时间： 2024-01-09 11:49:35

品牌	Logo	应用领域
爱特美尔 - ATMEL		可编程逻辑器件输入元件异步传输模式 PC ATM
页数	文件大小	规格书
19页	596K
描述
Highperformance EPLD

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技术参数
数据手册

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ATF1500AL-20JU 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
零件包装代码：	LPCC	包装说明：	QCCJ, TQFP44,.47SQ,32
针数：	44	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.31.00.01
Factory Lead Time：	1 week	风险等级：	5.55
Is Samacsys：	N	其他特性：	NO
系统内可编程：	NO	JESD-30 代码：	S-PQCC-J44
JESD-609代码：	e3	JTAG BST：	NO
长度：	16.586 mm	湿度敏感等级：	2
专用输入次数：		I/O 线路数量：	32
宏单元数：	32	端子数量：	44
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	0 DEDICATED INPUTS, 32 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	TQFP44,.47SQ,32	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	245
电源：	5 V	可编程逻辑类型：	FLASH PLD
传播延迟：	20 ns	认证状态：	Not Qualified
座面最大高度：	4.572 mm	子类别：	Programmable Logic Devices
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	16.586 mm
Base Number Matches：	1

ATF1500AL-20JU 数据手册

ATF1500A(L)

Each macrocell also generates a foldback logic term, which

goes to a regional bus. All signals within a regional bus are

connected to all 16 macrocells within the region.

Each output also has individual slew rate control. This may

be used to reduce system noise by slowing down outputs

that do not need to operate at maximum speed. Outputs

default to slow switching, and may be specified as fast

switching in the design file.

Cascade logic between macrocells in the ATF1500A allows

fast, efficient generation of complex logic functions. The

ATF1500A contains four such logic chains, each capable of

creating sum term logic with a fan-in of up to 40 product

terms.

Design Software Support

ATF1500A designs are supported by several third-party

tools. Automated fitters allow logic synthesis using a variety

of high-level description languages and formats.

Bus-friendly Pin-keeper Input and I/O’s

All Input and I/O pins on the ATF1500A have programma-

ble “pin-keeper” circuits. If activated, when any pin is driven

high or low and then subsequently left floating, it will stay at

that previous high or low level.

Input Diagram

V_CC

This circuitry prevents unused Input and I/O lines from

floating to intermediate voltage levels, which causes

unnecessary power consumption and system noise. The

keeper circuits eliminate the need for external pull-up resis-

tors and eliminate their DC power consumption.

INPUT

100K

Pin-keeper circuits can be disabled. Programming is con-

trolled in the logic design file. Once the pin-keeper circuits

are disabled, normal termination procedures are required

for unused inputs and I/Os.

ESD

PROTECTION

CIRCUIT

PROGRAMMABLE

OPTION

I/O Diagram

Speed/Power Management

The ATF1500A has several built-in speed and power man-

agement features. The ATF1500A contains circuitry that

automatically puts the device into a low-power standby

mode when no logic transitions are occurring. This not only

reduces power consumption during inactive periods, but

also provides proportional power savings for most applica-

tions running at system speeds below 10 MHz.

V_CC

DATA

I/O

V_CC

All ATF1500As also have an optional pin-controlled power-

down mode. In this mode, current drops to below 10 mA.

When the power-down option is selected, the PD pin is

used to power-down the part. The power-down option is

selected in the design source file. When enabled, the

device goes into power-down when the PD pin is high. In

the power-down mode, all internal logic signals are latched

and held, as are any enabled outputs. All pin transitions are

ignored until the PD is brought low. When the power-down

feature is enabled, the PD cannot be used as a logic input

or output. However, the PD pin’s macrocell may still

be used to generate buried foldback and cascade

logic signals.

100K

PROGRAMMABLE

OPTION

1 234 5 6 7...19

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