Datasheet > ATF1500ABV-15AJ

ATF1500ABV-15AJ

更新时间： 2024-01-02 20:57:57

品牌	Logo	应用领域
爱特美尔 - ATMEL		时钟输入元件可编程逻辑
页数	文件大小	规格书
15页	317K
描述
Flash PLD, 15ns, CMOS, PQFP44, 1 MM HEIGHT, PLASTIC, TQFP-44

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ATF1500ABV-15AJ 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	TQFP,
针数：	44	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.76
最大时钟频率：	52.6 MHz	JESD-30 代码：	S-PQFP-G44
JESD-609代码：	e3	长度：	10 mm
湿度敏感等级：	3	专用输入次数：
I/O 线路数量：	32	端子数量：	44
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	0 DEDICATED INPUTS, 32 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	TQFP
封装形状：	SQUARE	封装形式：	FLATPACK, THIN PROFILE
峰值回流温度（摄氏度）：	260	可编程逻辑类型：	FLASH PLD
传播延迟：	15 ns	认证状态：	Not Qualified
座面最大高度：	1.2 mm	最大供电电压：	5.5 V
最小供电电压：	2.7 V	标称供电电压：	3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	MATTE TIN
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	10 mm	Base Number Matches：	1

ATF1500ABV-15AJ 数据手册

ATF1500ABV

Power-up Reset

The ATF1500ABV’s registers are designed to reset during power-up. At a point delayed

slightly from V_CCcrossing V_RST, all registers will be reset to the low state. As a result, the reg-

istered output state will always be low on power-up.

This feature is critical for state machine initialization. However, due to the asynchronous

nature of reset and the uncertainty of how V_CCactually rises in the system, the following condi-

tions are required:

1. The V_CCrise must be monotonic, from below 0.7 volts.

2. Signals from which clocks are derived must remain stable during T_PR

3. After T_PRoccurs, all input and feedback setup times must be met before driving the

clock signal high.

Power-down

Mode

The ATF1500ABV includes an optional pin-controlled power-down feature. When this mode is

enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply

current is reduced to less than 10 µA. During power-down, all output data and internal logic

states are latched and held. Therefore, all registered and combinatorial output data remain

valid. Any outputs that were in a High-Z state at the onset of power-down will remain at

High-Z. During power-down, all input signals except the power-down pin are blocked. Input

and I/O hold latches remain active to ensure that pins do not float to indeterminate levels, fur-

ther reducing system power. The power-down pin feature is enabled in the logic design file.

Designs using the power-down pin may not use the PD pin logic array input. However, all

other PD pin macrocell resources may still be used, including the buried feedback and fold-

back product term array inputs.

Preload

The ATF1500ABV’s registers are provided with circuitry to allow loading of each register with

either a high or a low. This feature will simplify testing since any state can be forced into the

registers to control test sequencing. A JEDEC file with preload is generated when a source file

with preload vectors is compiled. Once downloaded, the JEDEC file preload sequence will be

done automatically when vectors are run by any approved programmers. The preload mode is

enabled by raising an input pin to a high voltage level. Contact Atmel PLD Applications for

PRELOAD pin assignments, timing and voltage requirements.

Parameter

Description

Typ

Max

Units

Power-up

Reset Time

µs

T_PR

Power-up

Reset

2.2

2.7

V_RST

Voltage

0723I–08/01

1...8 9 101112 13 14 15

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与ATF1500ABV-15AJ相关器件

型号	品牌	获取价格	描述	数据表
ATF1500ABV-15JC	ATMEL	获取价格	High- Performance EE PLD
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