Datasheet > ATF1500A-7AC

ATF1500A-7AC

更新时间： 2024-01-26 22:40:28

品牌	Logo	应用领域
爱特美尔 - ATMEL		可编程逻辑器件
页数	文件大小	规格书
16页	683K
描述
High Performance E2 PLD

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

ATF1500A-7AC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	LPCC	包装说明：	PLASTIC, MS-018AC, LCC-44
针数：	44	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.79
其他特性：	NO	最大时钟频率：	95 MHz
系统内可编程：	NO	JESD-30 代码：	S-PQCC-J44
JESD-609代码：	e0	JTAG BST：	NO
长度：	16.586 mm	湿度敏感等级：	2
专用输入次数：		I/O 线路数量：	32
宏单元数：	32	端子数量：	44
最高工作温度：	70 °C	最低工作温度：
组织：	0 DEDICATED INPUTS, 32 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC44,.7SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	225
电源：	5 V	可编程逻辑类型：	FLASH PLD
传播延迟：	7.5 ns	认证状态：	Not Qualified
座面最大高度：	4.572 mm	子类别：	Programmable Logic Devices
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	16.586 mm
Base Number Matches：	1

ATF1500A-7AC 数据手册

ATF1500A/AL

The ATF1500A has 32 bi-directional I/O pins and 4 dedi-

cated input pins. Each dedicated input pin can also serve

as a global control signal: register clock, register reset or

output enable. Each of these control signals can be

selected for use individually within each macrocell.

Speed/Power Management

The ATF1500A has several built-in speed and power man-

agement features. The ATF1500A contains circuitry that

automatically puts the device into a low power stand-by

mode when no logic transitions are occurring. This not only

reduces power consumption during inactive periods, but

also provides a proportional power savings for most appli-

cations running at system speeds below 10 MHz.

Each of the 32 logic macrocells generates a buried feed-

back, which goes to the global bus. Each input and I/O pin

also feeds into the global bus. Because of this global bus-

sing, each of these signals is always available to all 32

macrocells in the device.

All ATF1500As also have an optional pin-controlled power

down mode. In this mode, current drops to below 10 µA.

When the power down option is selected, the PD pin is

used to power down the part. The power down option is

selected in the design source file. When enabled, the

device goes into power down when the PD pin is high. In

the power down mode, all internal logic signals are latched

and held, as are any enabled outputs. All pin transitions are

ignored until the PD is brought low. When the power down

feature is enabled, the PD cannot be used as a logic input

or output. However, the PD pin's macrocell may still be

used to generate buried foldback and cascade logic sig-

nals.

Each macrocell also generates a foldback logic term, which

goes to a regional bus. All signals within a regional bus are

connected to all 16 macrocells within the region.

Cascade logic between macrocells in the ATF1500A allows

fast, efficient generation of complex logic functions. The

ATF1500A contains 4 such logic chains, each capable of

creating sum term logic with a fan in of up to 40 product

terms.

Bus Friendly Pin-Keeper Input and I/O’s

All Input and I/O pins on the ATF1500A have programma-

ble “data keeper” circuits. If activated, when any pin is

driven high or low and then subsequently left floating, it will

stay at that previous high or low level.

Each output also has individual slew rate control. This may

be used to reduce system noise by slowing down outputs

that do not need to operate at maximum speed. Outputs

default to slow switching, and may be specified as fast

switching in the design file.

This circuitry prevents unused Input and I/O lines from

floating to intermediate voltage levels, which cause unnec-

essary power consumption and system noise. The keeper

circuits eliminate the need for external pull-up resistors and

eliminate their DC power consumption.

Design Software Support

ATF1500A designs are supported by several 3rd party

tools. Automated fitters allow logic synthesis using a variety

of high level description languages and formats.

Pin-keeper circuits can be disabled. Programming is con-

trolled in the logic design file. Once the pin-keeper circuits

are disabled, normal termination procedures are required

for unused inputs and I/Os.

Input Diagram

I/O Diagram

V_CC

DATA

I/O

INPUT

100K

V_CC

ESD

PROTECTION

CIRCUIT

PROGRAMMABLE

OPTION

100K

PROGRAMMABLE

OPTION

1 234 5 6 7...16

下载PDF

与ATF1500A-7AC相关器件

型号	品牌	描述	获取价格	数据表
ATF1500A-7AL	ATMEL	Flash PLD, 7.5ns, CMOS, PQFP44, 10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, PLASTIC, MS-026ACB	获取价格
ATF1500A-7JC	ATMEL	High Performance E2 PLD	获取价格
ATF1500A-7JL	ATMEL	Flash PLD, 7.5ns, CMOS, PQCC44, PLASTIC, MS-018AC, LCC-44	获取价格
ATF1500ABV	ATMEL	High- Performance EE PLD	获取价格
ATF1500ABV-12AC	ATMEL	High- Performance EE PLD	获取价格
ATF1500ABV-12JC	ATMEL	High- Performance EE PLD	获取价格

与ATF1500A-7AC相关文章

STM32F030C6芯片介绍：主要参数分析、引脚配置说明、功耗及封装
2024-05-11

10
PCF8591数据手册解读：参数、引脚说明
2024-05-11

16
一文带你了解ss8050参数、引脚配置、应用指南
2024-05-11

7
深入解析AD7606高性能多通道模数转换器：资料手册参数分析
2024-05-10

9

产品中心

服务支持

精选活动

关于我们

帮助中心

ATF1500A-7AC

ATF1500A-7AC 技术参数

ATF1500A-7AC 数据手册

与ATF1500A-7AC相关器件

与ATF1500A-7AC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

ATF1500A-7AC

ATF1500A-7AC 技术参数

ATF1500A-7AC 数据手册

与ATF1500A-7AC相关器件

与ATF1500A-7AC相关文章

您还可以找

您在本页遇到什么问题？