Datasheet > ATA8210-WNQW

ATA8210-WNQW

更新时间： 2024-01-10 22:36:16

品牌	Logo	应用领域
爱特美尔 - ATMEL		电信电信集成电路
页数	文件大小	规格书
20页	776K
描述
Telecom Circuit, 1-Func, 5 X 5 MM, 0.50 MM PITCH, LEAD FREE, VQFN-32

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数据手册

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ATA8210-WNQW 技术参数

生命周期：	Active	包装说明：	HVQCCN,
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.7	JESD-30 代码：	S-XQCC-N32
长度：	5 mm	功能数量：	1
端子数量：	32	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	座面最大高度：	0.9 mm
标称供电电压：	3.6 V	表面贴装：	YES
电信集成电路类型：	TELECOM CIRCUIT	温度等级：	INDUSTRIAL
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	5 mm
Base Number Matches：	1

ATA8210-WNQW 数据手册

3.3

AVR Controller

3.3.1 AVR Controller Sub-System

The AVR^®controller sub-system consists of the AVR CPU core, its program memory, and a data bus with data memory and

peripheral blocks attached. The receive path also has its user interfaces connected to the data bus.

3.3.2 CPU Core

The main function of the CPU core is to ensure correct program execution. For this reason, the CPU core must be able to

access memories, perform calculations, control peripherals, and handle interrupts.

Figure 3-3. Overview of Architecture

Data Bus 8-bit

ROM

Flash

Program

Memory

Program

Counter

Status and

Control

Interrupt

Unit

SPI

32 x 8

General

Purpose

Registers

Unit

Instruction

Watchdog

Timer

Instruction

Decoder

ALU

Clock

Management

Control Lines

I/O Module 1

I/O Module n

PortN

Data

SRAM

EEPROM

In order to maximize performance and parallelism, the AVR uses a Harvard architecture—with separate memories and

buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one

instruction is being executed, the next instruction is prefetched from the program memory. This concept enables instructions

to be executed in every clock cycle. The program memory is in-system reprogrammable Flash memory and ROM.

The fast-access register file contains 32 × 8-bit general purpose working registers with a single clock cycle access time.

This allows a single-cycle arithmetic and logic unit (ALU) operation. In a typical ALU operation, two operands are output from

the register file, the operation is executed, and the result is stored back in the register file—in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing, enabling

efficient address calculations. One of these address pointers can also be used as an address pointer for lookup tables in the

Flash program memory. Referred to as ‘X,’ ‘Y,’ and ‘Z’ registers, these higher 16-bit function registers are described later in

this section.

ATA8210/ATA8215 [SUMMARY DATASHEET]

9344CS–INDCO–09/14

1...12 13 141516 17 18...20

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