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ATA6286-PNQW PDF预览

ATA6286-PNQW

更新时间: 2024-01-24 02:50:09
品牌 Logo 应用领域
爱特美尔 - ATMEL 电信集成电路电信电路
页数 文件大小 规格书
18页 245K
描述
TPMS Control and Transmitter IC

ATA6286-PNQW 技术参数

生命周期:Active包装说明:HVQCCN, LCC32,.2SQ,20
Reach Compliance Code:compliant风险等级:5.14
Is Samacsys:N数据速率:20 Mbps
JESD-30 代码:S-PQCC-N32长度:5 mm
功能数量:1端子数量:32
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装等效代码:LCC32,.2SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE座面最大高度:1 mm
标称供电电压:3 V表面贴装:YES
技术:CMOS电信集成电路类型:TELECOM CIRCUIT
温度等级:AUTOMOTIVE端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
宽度:5 mmBase Number Matches:1

ATA6286-PNQW 数据手册

 浏览型号ATA6286-PNQW的Datasheet PDF文件第9页浏览型号ATA6286-PNQW的Datasheet PDF文件第10页浏览型号ATA6286-PNQW的Datasheet PDF文件第11页浏览型号ATA6286-PNQW的Datasheet PDF文件第13页浏览型号ATA6286-PNQW的Datasheet PDF文件第14页浏览型号ATA6286-PNQW的Datasheet PDF文件第15页 
With ASK = High the power amplifier is switched on. This is used to perform the ASK modula-  
tion. During ASK modulation the IC is enabled with the FSK or the ENABLE pin.  
With FSK = Low the switch at pin XTO2 is closed, with FSK = High the switch is open. To  
achieve a faster start-up of the crystal oscillator, the FSK pin should be High during start-up of  
the XTO because the series resistance of the resonator seen from pin XTO1 is lower if the  
switch is off.  
The different modes of the ATA6285/ATA6286 are listed in Table 4-1.  
Table 4-1.  
ASK Pin  
Low  
Transmitter Part  
FSK Pin  
Low  
ENABLE Pin  
Low/open  
High  
Mode  
Power-down mode, FSK switch High Z  
Power-up, PA off, FSK switch Low Z  
Power-up, PA off, FSK switch High Z  
Power-up, PA on, FSK switch Low Z  
Power-up, PA on, FSK switch High Z  
Idle mode, FSK switch High Z  
Idle mode, FSK switch High Z  
Low  
Low  
Low  
High  
High/open  
High/open  
High/open  
Low  
High  
Low  
High  
High  
Low/High  
High  
High  
Low/High  
Low  
4.5.1  
Transmission with ENABLE = Open  
4.5.1.1  
ASK Mode  
The ATA6285/ATA6286 is activated by ENABLE = open, FSK = High, ASK = Low. The micro-  
controller is then switched to external clocking. After typically 0.6 ms, the CLK driver is activated  
automatically (i.e., the microcontroller waits until the XTO and CLK are ready). After another  
time period of 250 µs, the PLL is locked and ready to transmit. The output power can then be  
modulated by means of pin ASK. After transmission, ASK is switched to Low and the microcon-  
troller returns back to internal clocking. Then, the ATA6285/ATA6286 is switched to power-down  
mode with FSK = Low.  
Figure 4-2. Timing ASK Mode with ENABLE Open  
TXTO  
> 250 µs  
FSK  
ASK  
CLK  
Power-down  
Power-up,  
PA off  
Power-up, Power-up,  
Power-down  
PA on  
(High)  
PA off  
(Low)  
12  
ATA6285/ATA6286 [Preliminary]  
4958AS–AUTO–09/06  

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