3.4.1.1 Architectural Overview
This section discusses the AVR® core architecture in general. The main function of the CPU core is to ensure correct program
execution. Therefore it must be able to access memories, perform calculations, control peripherals, and handle interrupts.
Figure 3-5. Architectural Overview
Data Bus 8-bit
ROM
Flash
Program
Counter
Status and
Control
Interrupt
Unit
Program
Memory
SPI
Unit
32 x 8
General
Purpose
Registers
Instruction
Register
Watchdog
Timer
Instruction
Decoder
ALU
Clock
Management
Control Lines
I/O Module 1
I/O Module n
PortN
Data
SRAM
EEPROM
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses
for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is
being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In- System Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This
allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register
File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling
efficient address calculations. One of these address pointers can also be used as an address pointer for look up tables in Flash
program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register
operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information
about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address
space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit
instruction.
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