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ATA5830N-WNQW

更新时间: 2024-02-02 14:48:42
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
24页 2066K
描述
Telecom IC, PQCC32

ATA5830N-WNQW 技术参数

是否Rohs认证: 符合生命周期:Active
Reach Compliance Code:compliant风险等级:5.17
JESD-30 代码:S-PQCC-N32端子数量:32
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCN
封装等效代码:LCC32,.2SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER电源:2/3.3,5 V
认证状态:Not Qualified子类别:Other Telecom ICs
表面贴装:YES温度等级:INDUSTRIAL
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUADBase Number Matches:1

ATA5830N-WNQW 数据手册

 浏览型号ATA5830N-WNQW的Datasheet PDF文件第16页浏览型号ATA5830N-WNQW的Datasheet PDF文件第17页浏览型号ATA5830N-WNQW的Datasheet PDF文件第18页浏览型号ATA5830N-WNQW的Datasheet PDF文件第20页浏览型号ATA5830N-WNQW的Datasheet PDF文件第21页浏览型号ATA5830N-WNQW的Datasheet PDF文件第22页 
3.4.1.1 Architectural Overview  
This section discusses the AVR® core architecture in general. The main function of the CPU core is to ensure correct program  
execution. Therefore it must be able to access memories, perform calculations, control peripherals, and handle interrupts.  
Figure 3-5. Architectural Overview  
Data Bus 8-bit  
ROM  
Flash  
Program  
Counter  
Status and  
Control  
Interrupt  
Unit  
Program  
Memory  
SPI  
Unit  
32 x 8  
General  
Purpose  
Registers  
Instruction  
Register  
Watchdog  
Timer  
Instruction  
Decoder  
ALU  
Clock  
Management  
Control Lines  
I/O Module 1  
I/O Module n  
PortN  
Data  
SRAM  
EEPROM  
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses  
for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is  
being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed  
in every clock cycle. The program memory is In- System Reprogrammable Flash memory.  
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This  
allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register  
File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.  
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling  
efficient address calculations. One of these address pointers can also be used as an address pointer for look up tables in Flash  
program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.  
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register  
operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information  
about the result of the operation.  
Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address  
space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit  
instruction.  
Atmel ATA5830/ATA5830N [Summary DATASHEET]  
19  
9208FS–RKE–06/13  

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