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ATA5823 PDF预览

ATA5823

更新时间: 2024-02-13 22:36:55
品牌 Logo 应用领域
爱特美尔 - ATMEL /
页数 文件大小 规格书
98页 1355K
描述
UHF ASK/FSK Transceiver

ATA5823 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFN包装说明:HVQCCN, LCC48,.27SQ,20
针数:48Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.38JESD-30 代码:S-XQCC-N48
JESD-609代码:e3长度:7 mm
湿度敏感等级:2功能数量:1
端子数量:48最高工作温度:105 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC48,.27SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:2.5/5 V
认证状态:Not Qualified座面最大高度:1 mm
子类别:Other Telecom ICs标称供电电压:3 V
表面贴装:YES技术:CMOS
电信集成电路类型:TELECOM CIRCUIT温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:7 mm

ATA5823 数据手册

 浏览型号ATA5823的Datasheet PDF文件第5页浏览型号ATA5823的Datasheet PDF文件第6页浏览型号ATA5823的Datasheet PDF文件第7页浏览型号ATA5823的Datasheet PDF文件第9页浏览型号ATA5823的Datasheet PDF文件第10页浏览型号ATA5823的Datasheet PDF文件第11页 
5. Typical Key Fob Application for Full-duplex PEG  
Figure 5-1. Typical Key Fob Application for Full-duplex PEG, 433.92 MHz  
C4  
CDEM  
RSSI  
NC  
NC  
CS  
TEST3  
SCK  
C6  
C5  
NC  
RF_IN  
NC  
SDI_TMDI  
SDO_TMDO  
CLK  
C7  
AVCC  
Microcontroller  
433_N868  
NC  
R1  
ATA5823/ATA5824  
Loop antenna 2  
L2  
R_PWR  
PWR_H  
RF_OUT  
NC  
IRQ  
POUT  
VSINT  
NC  
VCC  
VSS  
20% overlap  
C8  
C9  
NC  
XTAL2  
13.25311 MHz  
C3  
C1  
Loop antenna 1  
C2  
C10  
+
Litihum-cell  
Figure 5-1 shows a typical 433.92 MHz PEG key fob application. The external components are  
10 capacitors, 1 resistor, 1 inductor and a crystal. C1 to C3 are 68 nF voltage supply blocking  
capacitors. C7 is a 10 nF supply blocking capacitor. C4 is a 15 nF fixed capacitor used for the  
internal quasi-peak detector and for the high-pass frequency of the data filter. C5, C6, C8 and C9  
are RF matching capacitors in the range of 1 pF to 33 pF. L2 is a feed inductor of about 120 nH.  
C10 is a 10 nF capacitor which is necessary to prevent that signals couple into the pin R_PWR,  
causing amplitude modulation of the output power and a spurious rise of the transmitted signal.  
R1 and C10 should be placed close to the R_PWR pin. A load capacitor of 9 pF for the crystal is  
integrated. R1 is typically 22 kand SETPWR is programmed to get an output power of –7 dBm  
in full-duplex mode and 5 dBm in half-duplex mode. The quality factor of the loop antenna 1 is  
only reduced by the quality factor of L2, the tolerances of C9 and C8 are thus important. The qual-  
ity factor of the loop antenna 2 is reduced to half due to the loading with the input impedance of  
RF_IN. With well designed loop antennas and the correct degree of overlapping, the isolation  
between RF_OUT and RF_IN is about 28 dB and the coupled output power from RF_OUT to  
RF_IN is about –35 dBm. The decoupling of two loop antennas situated close to each other is  
due to the effect that the magnetic flux from the part of loop antenna 1 that does not overlap and  
that of the overlapping part has an opposite direction. Depending on the relative position  
between the two antennas, a decoupling of 28 dB is achievable. Due to additional capacitive  
coupling between the loops the position of the components C5, C6 and C8, C9 are also important.  
The receive Sensitivity in full-duplex mode is reduced from –106 dBm without coupled  
RF-Power at RF_IN to –96 dBm with –35 dBm coupled RF power at RF_IN.  
8
ATA5823/ATA5824  
4829C–RKE–09/05  

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