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ATA5283_07 PDF预览

ATA5283_07

更新时间: 2022-04-23 23:00:11
品牌 Logo 应用领域
爱特美尔 - ATMEL /
页数 文件大小 规格书
14页 259K
描述
Interface IC for 125 kHz Wake-up Function

ATA5283_07 数据手册

 浏览型号ATA5283_07的Datasheet PDF文件第3页浏览型号ATA5283_07的Datasheet PDF文件第4页浏览型号ATA5283_07的Datasheet PDF文件第5页浏览型号ATA5283_07的Datasheet PDF文件第7页浏览型号ATA5283_07的Datasheet PDF文件第8页浏览型号ATA5283_07的Datasheet PDF文件第9页 
Figure 3-5. Turn Off Delay Time (toff) versus Antenna Q-Factor  
200  
180  
160  
140  
120  
f
= 125 kHz  
field  
typ.  
max.  
100  
80  
60  
min.  
40  
20  
0
0
10  
20  
30  
40  
50  
Q-factor  
3.5  
3.6  
3.7  
Data Output  
The data output N_DATA outputs the demodulated and digitized LF signal according to the  
envelope of the antenna input signal. In the standby mode the N_DATA output is disabled and  
set to level 1. It is enabled by the wake-up signal and it outputs 1 level if the IC detects the car-  
rier signal and a 0 level during the gaps (see Figure 3-1 on page 3).  
As the circuit does not check the received data (except the preamble), it is up to the user to  
choose the kind of encoding (pulse distance, Manchester, bi-phase...) wanted.  
Wake-up Signal  
The wake-up signal (N_WAKEUP) indicates that the ATA5283 has detected the end of a pream-  
ble signal and has left the standby mode. It can be used as a wake-up or a chip select signal for  
an external device (see Figure 3-1 on page 3).  
After a preamble is detected the first valid gap (Start Gap) sets the N_WAKEUP output to low  
and enables the data output N_DATA. The N_WAKEUP holds the low level until the IC is reset  
to the standby mode by a reset signal.  
Reset  
The IC is reset either by the internal POR circuit during a power on sequence or by a high pulse  
at the RESET pin. After the reset all internal counters are in the initial state and the IC is in the  
standby listen mode.  
The POR circuit generates a reset while the supply voltage VDD is below the power on reset  
threshold VPOR and release the function of the IC if VDD exceeds this threshold.  
A high signal at the RESET pin resets the complete circuit. If the IC is activated a reset signal is  
necessary to activate the standby listen mode.  
The RESET pin can also be used to hold the IC in a power down state. In this state the IC is out  
of operation and the current consumption is below the standby current.  
Note:  
The RESET pin is high impedance CMOS input. To avoid floating effects like undefined input  
states and malfunctions it should not be open.  
6
ATA5283  
4598H–AUTO–03/07  

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