Datasheet > AT71-ATM1M30M-B0

AT71-ATM1M30M-B0

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
26页	375K
描述
CameraLink Areascan Cameras

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数据手册

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AT71-ATM1M30M-B0 数据手册

[Preliminary] ATMOS -1M60/1M30

3. Camera Description

Figure 3-1. Camera Synoptic

Power Supplies

DC power

Data

CameraLink

Transceiver

CMOS

SENSOR

Strobe, LVAL

Sequencer

Controller

FVAL

Trigger

Camera Link

I/F

Shutter

Serial Line

Microcontroller

The camera is based on a single tap CMOS sensor which delivers a 12-bit digital video signal at

its output. An FPGA has been implemented for image processing (FPN column correction, con-

version LUT, contrast expansion). The camera is powered by a single DC power supply from

12V to 24V. The functional interface (data and control) is provided with the CameraLink inter-

face. The camera uses the base configuration of the CameraLink standard.

Note:

DVAL permanently tied to 1 (high) level.

Data can be delivered on a single channel or two de-multiplexed channels. The data format con-

figuration might be in 12-bit, 10-bit, or 8-bit. It is possible to use external triggers with the camera

(CC1 signal or TTL_IO trigger input) in different trigger modes see ”Synchronization Modes” on

page 6 The camera configuration and settings are done via the CameraLink serial communica-

tion. This interface is used for:

• Gain and offset setting

• Data output format

• Synchronization modes: free-run or external trigger modes

• Shutter time

• Test pattern generation

• Upload and download of correction data (FPN column correction, LUT)

5429B–IMAGE–04/05

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