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AT45DB161E-CCFU-T

更新时间： 2024-01-04 02:12:47
品牌 Logo 应用领域
爱特美尔 - ATMEL 闪存
页数 文件大小 规格书
70页 2255K
描述
16-Mbits DataFlash (with Extra 512-Kbits), 2.3V or 2.5V Minimum SPI Serial Flash Memory

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AT45DB161E-CCFU-T 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSOP包装说明：TSOP1, TSSOP28,.53,22
针数：28Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.51
风险等级：5.85其他特性：ORGANIZED AS 4096 BYTES PAGES OF 528 BYTES
最大时钟频率 (fCLK)：13 MHzJESD-30 代码：R-PDSO-G28
JESD-609代码：e0长度：11.8 mm
内存密度：16777216 bit内存集成电路类型：FLASH
内存宽度：1湿度敏感等级：3
功能数量：1端子数量：28
字数：16777216 words字数代码：16000000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：16MX1
封装主体材料：PLASTIC/EPOXY封装代码：TSOP1
封装等效代码：TSSOP28,.53,22封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE并行/串行：SERIAL
峰值回流温度（摄氏度）：240电源：3/3.3 V
编程电压：2.7 V认证状态：Not Qualified
座面最大高度：1.2 mm串行总线类型：SPI
最大待机电流：0.00001 A子类别：Flash Memories
最大压摆率：0.035 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.55 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
类型：NOR TYPE宽度：8 mm
写保护：HARDWARE

AT45DB161E-CCFU-T 数据手册

 浏览型号AT45DB161E-CCFU-T的Datasheet PDF文件第4页浏览型号AT45DB161E-CCFU-T的Datasheet PDF文件第5页浏览型号AT45DB161E-CCFU-T的Datasheet PDF文件第6页浏览型号AT45DB161E-CCFU-T的Datasheet PDF文件第8页浏览型号AT45DB161E-CCFU-T的Datasheet PDF文件第9页浏览型号AT45DB161E-CCFU-T的Datasheet PDF文件第10页 
5.  
Read Commands  
By specifying the appropriate opcode, data can be read from the main memory or from either one of the two SRAM data  
buffers. The DataFlash supports RapidS protocols for Mode 0 and Mode 3. Please see Section 25. Detailed Bit-level  
Read Waveforms: Atmel RapidS Mode 0/Mode 3 diagrams in this datasheet for details on the clock cycle sequences for  
each mode.  
5.1  
Continuous Array Read (Legacy Command: E8h Opcode)  
By supplying an initial starting address for the Main Memory Array, the Continuous Array Read command can be utilized  
to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional  
addressing information or control signals need to be provided. The DataFlash incorporates an internal address counter  
that will automatically increment on every clock cycle, allowing one Continuous Read operation without the need of  
additional address sequenced. To perform a Continuous Read from the standard DataFlash page size (528 bytes), an  
opcode of E8h must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte  
address sequence) and four dummy bytes. The first 12 bits (PA11 - PA0) of the 22-bit address sequence specify which  
page of the Main Memory Array to read and the last 10 bits (BA9 - BA0) of the 22-bit address sequence specify the  
starting byte address within the page. To perform a Continuous Read from the binary page size (512 bytes), an opcode of  
E8h must be clocked into the device followed by three address bytes and four dummy bytes. The first  
12 bits (A20 - A9) of the 21-bit sequence specify which page of the Main Memory Array to read and the last nine bits  
(A8 - A0) of the 21-bit address sequence specify the starting byte address within the page. The dummy bytes that follow  
the address bytes are needed to initialize the read operation. Following the dummy bytes, additional clock pulses on the  
SCK pin will result in data being output on the SO (serial output) pin.  
The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of  
data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue  
reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from  
the end of one page to the beginning of the next page). When the last bit in the Main Memory Array has been read, the  
device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no  
delays will be incurred when wrapping around from the end of the array to the beginning of the array.  
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum  
SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The Continuous Array Read  
bypasses the data buffers and leaves the contents of the buffers unchanged.  
Note:  
This command is not recommended for new designs.  
5.2  
Continuous Array Read (High Frequency Mode: 1Bh Opcode)  
This command can be used with the serial interface to read the Main Memory Array sequentially in very High-Speed (HS)  
mode for any clock frequency up to the maximum specified by fCAR1. To perform a Continuous Read Array with the  
standard DataFlash page size (528 bytes), the CS must first be asserted then an opcode 1Bh must be clocked into the  
device followed by three address bytes and two dummy bytes. The first 12 bits (PA11 - PA0) of the 22-bit address  
sequence specify which page of the Main Memory Array to read and the last 10 bits (BA9 - BA0) of the 22-bit address  
sequence specify the starting byte address within the page. To perform a Continuous Read with the binary page size  
(512 bytes), the opcode 1Bh must be clocked into the device followed by three address bytes (A20 - A0) and two dummy  
bytes. Following the dummy bytes, additional clock pulses on the SCK pin will result in data being output on the SO  
(Serial Output) pin.  
The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of  
data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue  
reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover  
from the end of one page to the beginning of the next page). When the last bit in the Main Memory Array has been read,  
the device will continue reading back at the beginning of the first page of memory. As with crossing over page  
boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array.  
Atmel AT45DB161E [PRELIMINARY DATASHEET]  
7
8782A–DFLASH–3/12  
1...45678910...70

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