Atmel AT45DB161D
5.
Device Operation
The device operation is controlled by instructions from the host processor. The list of instructions and their
associated opcodes are contained in Table 15-1 on page 27 through Table 15-7 on page 30. A valid instruction
starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory
address location. While the CS pin is low, toggling the SCK pin controls the loading of the opcode and the desired
buffer or main memory address location through the SI (serial input) pin. All instructions, addresses, and data are
transferred with the most significant bit (MSB) first.
Buffer addressing for standard Atmel® DataFlash page size (528-bytes) is referenced in the datasheet using the
terminology BFA9 - BFA0 to denote the 10 address bits required to designate a byte address within a buffer. Main
memory addressing is referenced using the terminology PA11 - PA0 and BA9 - BA0, where PA11 - PA0 denotes
the 12 address bits required to designate a page address and BA9 - BA0 denotes the 10 address bits required to
designate a byte address within the page.
For “Power of 2” binary page size (512-bytes) the Buffer addressing is referenced in the datasheet using the
conventional terminology BFA8 - BFA0 to denote the nine address bits required to designate a byte address within
a buffer. Main memory addressing is referenced using the terminology A20 - A0, where A20 - A9 denotes the 12
address bits required to designate a page address and A8 - A0 denotes the nine address bits required to designate
a byte address within a page.
6.
Read Commands
By specifying the appropriate opcode, data can be read from the main memory or from either one of the two SRAM
data buffers. The Atmel DataFlash supports Atmel RapidS™ protocols for Mode 0 and Mode 3. Please refer to the
“Detailed Bit-level Read Timing” diagrams in this datasheet for details on the clock cycle sequences for each
mode.
6.1
Continuous Array Read (Legacy Command: E8H): Up to 66MHz
By supplying an initial starting address for the main memory array, the Continuous Array Read command can be
utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no
additional addressing information or control signals need to be provided. The DataFlash incorporates an internal
address counter that will automatically increment on every clock cycle, allowing one continuous read operation
without the need of additional address sequences. To perform a continuous read from the standard DataFlash
page size (528-bytes), an opcode of E8H must be clocked into the device followed by three address bytes (which
comprise the 24-bit page and byte address sequence) and four don’t care bytes. The first 12 bits (PA11 - PA0) of
the 22-bit address sequence specify which page of the main memory array to read, and the last 10 bits (BA9 -
BA0) of the 22-bit address sequence specify the starting byte address within the page. To perform a continuous
read from the binary page size (512-bytes), the opcode (E8H) must be clocked into the device followed by three
address bytes and four don’t care bytes. The first 12 bits (A20 - A9) of the 21-bits sequence specify which page of
the main memory array to read, and the last nine bits (A8 - A0) of the 21-bits address sequence specify the starting
byte address within the page. The don’t care bytes that follow the address bytes are needed to initialize the read
operation. Following the don’t care bytes, additional clock pulses on the SCK pin will result in data being output on
the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care bytes, and the
reading of data. When the end of a page in main memory is reached during a Continuous Array Read, the device
will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover
(the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory
array has been read, the device will continue reading back at the beginning of the first page of memory. As with
crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the
beginning of the array.
5
3500N–DFLASH–05/10
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