5秒后页面跳转
AT25EU0081A PDF预览

AT25EU0081A

更新时间: 2024-05-07 20:39:22
品牌 Logo 应用领域
瑞萨 - RENESAS 闪存
页数 文件大小 规格书
63页 2379K
描述
8 Mbit 超低功耗串行闪存

AT25EU0081A 数据手册

 浏览型号AT25EU0081A的Datasheet PDF文件第3页浏览型号AT25EU0081A的Datasheet PDF文件第4页浏览型号AT25EU0081A的Datasheet PDF文件第5页浏览型号AT25EU0081A的Datasheet PDF文件第7页浏览型号AT25EU0081A的Datasheet PDF文件第8页浏览型号AT25EU0081A的Datasheet PDF文件第9页 
AT25EU0081A Datasheet  
2. Package Types and Pinouts  
2.1  
Pin Assignments  
CS  
1
2
3
4
8
VCC  
SO (IO1)  
WP (IO2)  
GND  
HOLD (IO3)  
SCK  
7
6
5
SI (IO0)  
Figure 2. AT25EU0081A Pin Assignments, Eight-pin SOP 150-mil and 208-mil (Top View)  
CS  
SO (IO1)  
WP (IO2)  
GND  
1
2
3
4
8
VCC  
HOLD (IO3)  
SCK  
7
6
5
SI (IO0)  
Figure 3. AT25EU0081A Pad Assignments, Eight-pad UDFN 2x3 mm (Top View)  
During all operations, V must be held stable and within the specified valid range: V (min) to V (max).  
CC  
CC  
CC  
All of the input and output signals must be held high or low (according to voltages of V , V , V , or V ; see  
IH  
OH  
IL  
OL  
Section 7.6, AC Characteristics).  
2.2  
Pin Descriptions  
Table 1. Pin Descriptions  
Name and Function  
Asserted  
State  
Symbol  
Type  
CHIP SELECT  
Asserting the CS pin selects the device. When the CS pin is deasserted, the device is  
deselected and normally be placed in standby mode (all input signals are ignored, and  
all output signals are high impedance).  
Unless an internal Program, Erase, or Write Status Registers embedded operation is in  
progress, the device is in the Standby Power mode. Driving the CS input to low enables  
the device, placing it in the Active Power mode. After power-up, a falling edge on CS is  
required before the start of any command.  
CS  
Low  
Input  
A high-to-low transition on the CS pin is required to start an operation; a low-to-high  
transition is required to end an operation. When ending an internally self-timed  
operation, such as a program or erase cycle, the device does not enter the standby  
mode until the operation is complete.  
To ensure correct power-up sequencing, it is recommended to add a 10k Ohm pull-up  
resistor from CS to V . This ensures CS ramps together with V during power-up.  
CC  
CC  
SERIAL CLOCK  
This pin provides a clock to the device. Command, address, and input data present on  
the SI pin is latched in on the rising edge of SCK, while output data on the SO pin is  
clocked out on the falling edge of SCK.  
SCK  
-
Input  
DS-AT25EU0081A-213 Rev. C  
Jan 5, 2024  
Page 6  
© 2024 Renesas Electronics  

与AT25EU0081A相关器件

型号 品牌 描述 获取价格 数据表
AT25F1024 ATMEL SPI Serial Memory

获取价格

AT25F1024_14 ATMEL Byte Mode and 256-byte Page Mode for Program Operations

获取价格

AT25F1024-10UC-2.7 ATMEL Flash, 128KX8, PBGA8, DBGA-8

获取价格

AT25F1024-10UI-2.7 ETC SPI Serial EEPROM

获取价格

AT25F1024-10UI-27 ATMEL Flash, 128KX8, PBGA8, DBGA-8

获取价格

AT25F1024A ATMEL SPI Serial Memory

获取价格