AT25EU0081A Datasheet
2. Package Types and Pinouts
2.1
Pin Assignments
CS
1
2
3
4
8
VCC
SO (IO1)
WP (IO2)
GND
HOLD (IO3)
SCK
7
6
5
SI (IO0)
Figure 2. AT25EU0081A Pin Assignments, Eight-pin SOP 150-mil and 208-mil (Top View)
CS
SO (IO1)
WP (IO2)
GND
1
2
3
4
8
VCC
HOLD (IO3)
SCK
7
6
5
SI (IO0)
Figure 3. AT25EU0081A Pad Assignments, Eight-pad UDFN 2x3 mm (Top View)
During all operations, V must be held stable and within the specified valid range: V (min) to V (max).
CC
CC
CC
All of the input and output signals must be held high or low (according to voltages of V , V , V , or V ; see
IH
OH
IL
OL
Section 7.6, AC Characteristics).
2.2
Pin Descriptions
Table 1. Pin Descriptions
Name and Function
Asserted
State
Symbol
Type
CHIP SELECT
Asserting the CS pin selects the device. When the CS pin is deasserted, the device is
deselected and normally be placed in standby mode (all input signals are ignored, and
all output signals are high impedance).
Unless an internal Program, Erase, or Write Status Registers embedded operation is in
progress, the device is in the Standby Power mode. Driving the CS input to low enables
the device, placing it in the Active Power mode. After power-up, a falling edge on CS is
required before the start of any command.
CS
Low
Input
A high-to-low transition on the CS pin is required to start an operation; a low-to-high
transition is required to end an operation. When ending an internally self-timed
operation, such as a program or erase cycle, the device does not enter the standby
mode until the operation is complete.
To ensure correct power-up sequencing, it is recommended to add a 10k Ohm pull-up
resistor from CS to V . This ensures CS ramps together with V during power-up.
CC
CC
SERIAL CLOCK
This pin provides a clock to the device. Command, address, and input data present on
the SI pin is latched in on the rising edge of SCK, while output data on the SO pin is
clocked out on the falling edge of SCK.
SCK
-
Input
DS-AT25EU0081A-213 Rev. C
Jan 5, 2024
Page 6
© 2024 Renesas Electronics