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AT25F1024N-10SI-2.7 PDF预览

AT25F1024N-10SI-2.7

更新时间: 2024-02-11 05:57:44
品牌 Logo 应用领域
爱特美尔 - ATMEL 存储
页数 文件大小 规格书
17页 152K
描述
SPI Serial Memory

AT25F1024N-10SI-2.7 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:5.77
最大时钟频率 (fCLK):20 MHz耐久性:10000 Write/Erase Cycles
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.9 mm内存密度:1048576 bit
内存集成电路类型:FLASH内存宽度:8
湿度敏感等级:1功能数量:1
端子数量:8字数:131072 words
字数代码:128000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:128KX8封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:SERIAL峰值回流温度(摄氏度):240
电源:3/3.3 V编程电压:2.7 V
认证状态:Not Qualified座面最大高度:1.75 mm
串行总线类型:SPI最大待机电流:0.00001 A
子类别:Flash Memories最大压摆率:0.03 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30类型:NOR TYPE
宽度:3.9 mm最长写入周期时间 (tWC):10 ms
写保护:HARDWARE/SOFTWAREBase Number Matches:1

AT25F1024N-10SI-2.7 数据手册

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Features  
Serial Peripheral Interface (SPI) Compatible  
Supports SPI Modes 0 (0,0) and 3 (1,1)  
20 MHz Clock Rate  
Byte Mode and 256-byte Page Mode for Program Operations  
Sector Architecture:  
– Two Sectors with 32K Bytes Each (512K)  
– Four Sectors with 32K Bytes Each (1M)  
– 128 Pages per Sector  
Product Identification Mode  
Low-voltage Operation  
– 2.7 (VCC = 2.7V to 3.6V)  
Sector Write Protection  
Write Protect (WP) Pin and Write Disable Instructions for  
both Hardware and Software Data Protection  
Self-timed Program Cycle (60 µs/Byte Typical)  
Self-timed Sector Erase Cycle (1 second/Sector Typical)  
Single Cycle Reprogramming (Erase and Program) for Status Register  
High Reliability  
SPI Serial  
Memory  
512K (65,536 x 8)  
1M (131,072 x 8)  
– Endurance: 10,000 Write Cycles Typical  
8-lead JEDEC SOIC  
AT25F512  
Description  
AT25F1024  
The AT25F512/1024 provides 524,288/1,048,576 bits of serial reprogrammable Flash  
memory organized as 65,536/131,072 words of 8 bits each. The device is optimized  
for use in many industrial and commercial applications where low-power and low-volt-  
age operation are essential. The AT25F512/1024 is available in a space-saving 8-lead  
JEDEC SOIC package.  
The AT25F512/1024 is enabled through the Chip Select pin (CS) and accessed via a  
3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and  
Serial Clock (SCK). All write cycles are completely self-timed.  
BLOCK WRITE protection for top 1/4, top 1/2 or the entire memory array (1M) or  
entire memory array (512K) is enabled by programming the status register. Separate  
write enable and write disable instructions are provided for additional data protection.  
Hardware data protection is provided via the WP pin to protect against inadvertent  
write attempts to the status register. The HOLD pin may be used to suspend any serial  
communication without resetting the serial sequence.  
Pin Configurations  
8-lead SOIC  
Pin Name  
Function  
CS  
SO  
1
2
3
4
8
7
6
5
VCC  
HOLD  
SCK  
SI  
CS  
Chip Select  
WP  
SCK  
SI  
Serial Data Clock  
Serial Data Input  
Serial Data Output  
Ground  
GND  
SO  
GND  
VCC  
WP  
Power Supply  
Write Protect  
HOLD  
Suspends Serial Input  
Rev. 1440M–SEEPR–7/03  

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