Datasheet > AS91L1001BU10L100IF

AS91L1001BU10L100IF

更新时间： 2022-11-25 11:21:28

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
28页	568K
描述
The AS91L1006BU is a one to 6-port JTAG gateway

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AS91L1001BU10L100IF 数据手册

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July 2004

AS91L1006BU

Signal Description

TYPE

Stable state

after port/reset

PIN NAME

NUMBER NUMBER

LQFP

DESCRIPTION

FPBGA

LSP1_TCK

OUT

IEEE1149.1 Test Clock on LSP 1

when PASS_THRU_ENABLE is

HIGH.

Buffered version

of signal present

on primary TCK

Pin is in Pass-Through mode when

PASS_THRU_ENABLE = 0 and

PASS_THRU_SEL[2:0] = 000.

This pin is tri-stated for all other

combinations.

IEEE1149.1 Test Mode Select on

LSP 1 when PASS_THRU_ENABLE

is HIGH.

LSP1_TMS

Logic '1'

Pin is in Pass-Through mode when

PASS_THRU_ENABLE = 0 and

PASS_THRU_SEL[2:0] = 000.

This pin is tri-stated for all other

combinations.

IEEE1149.1 Test Data Out on LSP 1 Logic '1'

when PASS_THRU_ENABLE is

HIGH.

LSP1_TDO

Pin is in Pass-Through mode when

PASS_THRU_ENABLE = 0 and

PASS_THRU_SEL[2:0] = 000.

This pin is tri-stated for all other

combinations.

LSP1_TDI

IEEE1149.1 Test Data In on LSP 1

when PASS_THRU_ENABLE is

HIGH.

Pin is in Pass-Through mode when

PASS_THRU_ENABLE = 0 and

PASS_THRU_SEL[2:0] = 000.

IEEE1149.1 Test Reset on LSP 1

when PASS_THRU_ENABLE is

HIGH.

LSP1_TRST

OUT

Buffered version

of signal present

on primary TRST

Pin is in Pass-Through mode when

PASS_THRU_ENABLE = 0 and

PASS_THRU_SEL[2:0] = 000.

This pin is tri-stated for all other

combinations.

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