5秒后页面跳转
捷配首页

Datasheet > AS91L1001BU10L100CF
AS91L1001BU10L100CF PDF预览

AS91L1001BU10L100CF

更新时间： 2022-11-25 11:21:28
品牌 Logo 应用领域
其他 - ETC /
页数 文件大小 规格书
28页 568K
描述
The AS91L1006BU is a one to 6-port JTAG gateway

阅读下载

获取价格

AS91L1001BU10L100CF 数据手册

 浏览型号AS91L1001BU10L100CF的Datasheet PDF文件第4页浏览型号AS91L1001BU10L100CF的Datasheet PDF文件第5页浏览型号AS91L1001BU10L100CF的Datasheet PDF文件第6页浏览型号AS91L1001BU10L100CF的Datasheet PDF文件第8页浏览型号AS91L1001BU10L100CF的Datasheet PDF文件第9页浏览型号AS91L1001BU10L100CF的Datasheet PDF文件第10页 
July 2004  
AS91L1006BU  
internal registers to be reset. In order to enable  
SELF_TEST Register  
The AS91L1006BU device supports a  
async reset tests on LSPs, the test tool should  
instruct the device to toggle the LSP reset pins  
while maintaining the set up information in the  
AS91L1006BU. When the instruction is loaded  
into the AS91L1006BU instruction register, a  
single bit data register is connected as the data  
register which is always reset to logic zero when  
the TAP state machine enters Capture-DR. This  
will cause the LSP TRST pins to pulse low for one  
TCK cycle, during the Update-DR phase.  
single output pin that can be controlled via the  
IEEE1149.1 interface. When the instruction is  
loaded into the AS91L1006BU instruction register,  
a single bit data register is connected which is  
always reset to logic zero when the TAP state  
machine enters Capture-DR. This will cause the  
SELF_TEST pin to pulse low for one cycle of TCK,  
during the Update-DR phase. This low going pulse  
can be used to initiate self-tests on PCB’s in a rack  
via the JTAG interface.  
AUTOWR Register  
This is a 6-bit register that controls the pass-  
through of the JTAG Technologies AutoWR™  
signal to any LSP. The register is reset to all  
zeros when entering the Test-Logic-Reset state.  
LSP_ASYNC_RST Register  
The AS91L1006BU device supports async  
reset tests on the devices connected to the LSPs.  
The standard method of performing these tests by  
utilizing the primary TRST pin cannot be used as it  
will cause the AS91L1006BU to deselect and its  
ꢁNote: The MCGR is reset to 00 upon receiving TRST or the entering of the  
Test-Logic-Reset state  
AutoWr  
Register AutoWr  
(Bit 2 –  
Bit 0)  
000  
LSP 3  
LSP 2  
AutoWr  
Signal  
LSP 1  
AutoWr  
Signal  
AutoWr  
Register  
(Bit 5 – Bit  
3)  
LSP 6  
AutoWr  
Signal  
LSP 5  
AutoWr  
Signal  
LSP 4  
AutoWr  
Signal  
Signal  
High Z  
High Z  
High Z  
Active  
High Z  
High Z  
Active  
Active  
High Z  
Active  
Active  
High Z  
Active  
High Z  
Active  
000  
High Z  
High Z  
High Z  
Active  
Active  
Active  
Active  
High Z  
High Z  
Active  
High Z  
High Z  
Active  
Active  
High Z  
Active  
Active  
High Z  
Active  
High Z  
Active  
001  
011  
100  
101  
110  
111  
High Z  
High Z  
Active  
Active  
Active  
Active  
001  
011  
100  
101  
110  
111  
Table 6 - AUTOWR Register Mapping  
www.alsc.com  
Alliance Semiconductor  
2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved.  
7
1...45678910...28

下载PDF

与AS91L1001BU10L100CF相关器件

型号 品牌 描述 获取价格 数据表
AS91L1001BU10L100CG ETC The AS91L1006BU is a one to 6-port JTAG gateway

获取价格
AS91L1001BU10L100I ETC The AS91L1006BU is a one to 6-port JTAG gateway

获取价格
AS91L1001BU10L100IF ETC The AS91L1006BU is a one to 6-port JTAG gateway

获取价格
AS91L1001BU10L100IG ETC The AS91L1006BU is a one to 6-port JTAG gateway

获取价格
AS91L1001BU40F100C ETC The AS91L1006BU is a one to 6-port JTAG gateway

获取价格
AS91L1001BU40F100CF ETC The AS91L1006BU is a one to 6-port JTAG gateway

获取价格

与AS91L1001BU10L100CF相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证