Datasheet > AS91L1001BU10L100CF

AS91L1001BU10L100CF

更新时间： 2022-11-25 11:21:28

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
28页	568K
描述
The AS91L1006BU is a one to 6-port JTAG gateway

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July 2004

AS91L1006BU

AS91L1006BU device Register descriptions

Bypass Register

It is a mandatory single bit register that can

Multi-Cast Group Register

This 2-bit data register enables the host

be connected between PRIM_TDI and PRIM_TDO

of the AS91L1006BU device.

system to place the AS91L1006BU into one of

four distinct addressable groups.

MCGR Register Bits Binary Selection Address

MCGR GROUP

GRP0

[1..0]

XX111100

XX111101

XX111110

XX111111

GRP1

GRP2

GRP3

Table 5 - Multicast Group Register Mapping

ꢁNote: The MCGR is reset to 00 upon receiving TRST or the entering of the Test-Logic-Reset

state.

Bits 12 to 27 indicate the part number of the

device: “0000000000010000”

IDCODE Register

It is an optional 32-bit register that can be

Bits 28 to 31 indicate the revision of the device:

“0000”

connected between PRIM_TDI and PRIM_TDO of

the AS91L1006BU device. The contents of the

IDCODE register will be loaded with the following

data when the AS91L1006BU enters Test-Logic-

Reset or passes through Capture-IR:

USERCODE Register

The USERCODE is an 8-bit register that can

be addressed via standard IEEE1149.1

commands, which are automatically generated by

third party test tools. AS91L1006BU returns all

zeroes if read from this registerUSERUSER and

does have the ability to write into this register.

"00000000000000001000001101101111"

Bits 0 to 11 indicate ALSC Jedec ID value of:

“001101101111”

ꢁ

* The AS91L1006BU is a complete second source and pin for pin replacement of the

Firecron JTS06BU device.

www.alsc.com

Alliance Semiconductor

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