Datasheet > AS91L1001BU10L100CF

AS91L1001BU10L100CF

更新时间： 2024-02-29 10:43:16

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The AS91L1006BU is a one to 6-port JTAG gateway

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AS91L1001BU10L100CF 数据手册

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July 2004

AS91L1006BU

Pass Through Support within the AS91L1006BU Device

The AS91L1006BU device supports a

Pass-Through mode where the primary or master

IEEE1149.1 JTAG signals can be routed to any

one of the LSPs. When this mode is activated, the

“Debug Enable” signal for that LSP will go active,

which can be used to place a processor such as

the MPC8260 into BDM (Background Debug

mode), if required. If no processors are present in

the LSP, the Pass-Through mode can be used to

assist in the generation of the test vectors or

memory tests for the devices that are linked into

the selected LSP. The pass-through feature has

the effect of simplifying the test vector generation

for the LSP, as it also has the effect of removing

the AS91L1006BU device from the test vector

generation process.

PASS_THRU_Enable PASS_THRU_SEL(2) PASS_THRU_SEL(1) PASS_THRU_SEL(0) Active LSP

High

Low

Normal

Operation

Low

High

Low

High

Low

High

Low

High

Low

High

LSP1

LSP2

LSP3

LSP4

LSP5

LSP6

Table 8 - Pass through mode in AS91L1006BU

ꢁNote: When PASS_THRU_ENABLE is deasserted (logic “1”), then the LSPs are under

control of the AS91L1006BU device logic. When PASS_THRU_ENABLE is asserted (logic

“0”) and if an invalid combination is presented on the PASS_THRU_SEL lines, then all LSPs

are tri-stated.

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