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AS7C251MNTD32A-167TQC PDF预览

AS7C251MNTD32A-167TQC

更新时间： 2024-01-08 00:32:08
品牌 Logo 应用领域
ALSC 时钟静态存储器内存集成电路
页数 文件大小 规格书
22页 453K
描述
ZBT SRAM, 1MX32, 7.5ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100

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AS7C251MNTD32A-167TQC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP, QFP100,.63X.87
针数：100Reach Compliance Code：unknown
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.85最长访问时间：7.5 ns
其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：167 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：33554432 bit内存集成电路类型：ZBT SRAM
内存宽度：32功能数量：1
端子数量：100字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：1MX32输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.06 A最小待机电流：2.38 V
子类别：SRAMs最大压摆率：0.35 mA
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm

AS7C251MNTD32A-167TQC 数据手册

 浏览型号AS7C251MNTD32A-167TQC的Datasheet PDF文件第3页浏览型号AS7C251MNTD32A-167TQC的Datasheet PDF文件第4页浏览型号AS7C251MNTD32A-167TQC的Datasheet PDF文件第5页浏览型号AS7C251MNTD32A-167TQC的Datasheet PDF文件第7页浏览型号AS7C251MNTD32A-167TQC的Datasheet PDF文件第8页浏览型号AS7C251MNTD32A-167TQC的Datasheet PDF文件第9页 
AS7C251MNTD32A  
AS7C251MNTD36A  
®
Burst order  
Interleaved burst order LBO = 1  
A1 A0 A1 A0 A1 A0 A1 A0  
Linear burst order LBO = 0  
A1 A0 A1 A0 A1 A0 A1 A0  
Starting address  
First increment  
0 0  
0 1  
0 1  
0 0  
1 1  
1 0  
1 0  
1 1  
0 0  
0 1  
1 1  
1 0  
0 1  
0 0  
Starting Address  
First increment  
0 0  
0 1  
0 1  
1 0  
1 1  
0 0  
1 0  
1 1  
0 0  
0 1  
1 1  
0 0  
0 1  
1 0  
Second increment 1 0  
Third increment 1 1  
Second increment 1 0  
Third increment  
1 1  
Synchronous truth table[5,6,7,8,9]  
Address  
CE0 CE1 CE2 ADV/LD R/W  
BWn  
X
OE CEN source  
CLK  
Operation  
DQ  
High-Z  
High-Z  
High-Z  
High-Z  
Q
Notes  
H
X
X
X
L
X
X
L
X
H
X
X
L
L
L
L
H
L
H
L
H
L
H
L
X
X
X
X
H
X
H
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
NA  
NA  
NA  
NA  
L to H  
L to H  
L to H  
L to H  
DESELECT Cycle  
DESELECT Cycle  
DESELECT Cycle  
X
X
X
H
X
H
X
H
X
H
X
CONTINUE DESELECT Cycle  
READ Cycle (Begin Burst)  
READ Cycle (Continue Burst)  
1
X
External L to H  
Next L to H  
X
L
X
L
X
L
Q
1,10  
2
X
H
H
X
X
X
External L to H NOP/DUMMY READ (Begin Burst) High-Z  
X
L
X
L
X
Next L to H DUMMY READ (Continue Burst) High-Z 1,2,10  
L
External L to H  
WRITE CYCLE (Begin Burst)  
D
D
3
X
L
X
L
X
L
L
Next L to H WRITE CYCLE (Continue Burst)  
1,3,10  
H
External L to H NOP/WRITE ABORT (Begin Burst) High-Z 2,3  
1,2,3,  
X
X
X
H
X
H
X
X
L
Next L to H WRITE ABORT (Continue Burst)  
High-Z  
10  
X
X
X
X
X
X
H
Current L to H  
INHIBIT CLOCK  
-
4
Key: X = Don’t Care, H = HIGH, L = LOW. BWn = H means all byte write signals (BWa, BWb, BWc, and BWd) are HIGH. BWn = L means one or  
more byte write signals are LOW.  
Notes:  
1 CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chose in the initial  
BEGIN BURST cycle. A CONINUE DESELECT cycle can only be entered if a DESELECT CYCLE is executed first.  
2 DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a  
WRITE command is given, but no operation is performed.  
3 OE may be wired LOW to minimize the number of control signal to the SRAM. The device will automatically turn off the output drivers during a WRITE  
cycle. OE may be used when the bus turn-on and turn-off times do not meet an application’s requirements.  
4 If an INHIBIT CLOCK command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will  
remain in High-Z. No WRITE operations will be performed during the INHIBIT CLOCK cycle.  
5 BWa enables WRITEs to byte “a” (DQa pins/balls); BWb enables WRITEs to byte “b” (DQb pins/balls); BWc enables WRITEs to byte “c” (DQc pins/  
balls); BWd enables WRITEs to byte “d” (DQd pins/balls).  
6 All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.  
7 Wait states are inserted by setting CEN HIGH.  
8 This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.  
9 The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE.  
10 The address counter is incremented for all CONTINUE BURST cycles.  
4/26/04, V 1.0  
Alliance Semiconductor  
P. 6 of 22  
1...3456789...22

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AS7C251MNTD32A-200BC ALSC ZBT SRAM, 1MX32, 6.5ns, CMOS, PBGA165, BGA-165

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