AS4C64M4SA-7TCN
AS4C64M4SA-6TIN
64M x 4 bit Synchronous DRAM (SDRAM)
Advance (Rev. 1.0, Jun. /2017)
Overview
Features
The AS4C64M4SA SDRAM is
a
high-speed
Fast access time from clock: 5/5.4 ns
Fast clock rate: 166/143 MHz
Fully synchronous operation
Internal pipelined architecture
16M word x 4-bit x 4-bank
Programmable Mode registers
- CAS Latency: 2 or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: Sequential or Interleaved
- Burst stop function
CMOS synchronous DRAM containing 256 Mbits. It
is internally configured as 4 Banks of 16M word x 4
DRAM with a synchronous interface (all signals are
registered on the positive edge of the clock signal,
CLK). Read and write accesses to the SDRAM are
burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with
the registration of a Bank Activate command which is
then followed by a Read or Write command.
Auto Refresh and Self Refresh
8192 refresh cycles/64ms
CKE power down mode
Single +3.3V ±0.3V power supply
Operating Temperature:
The AS4C64M4SA provides for programmable
Read or Write burst lengths of 1, 2, 4, 8, or full page,
with a burst termination option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence. The refresh functions, either Auto or Self
Refresh are easy to use. By having a programmable
mode register, the system can choose the most
suitable modes to maximize its performance. These
devices are well suited for applications requiring high
memory bandwidth and particularly well suited to
Commercial: TA = 0~70°C
Industrial: TA = -40~85°C
Interface: LVTTL
54-pin 400 mil plastic TSOP II package
- Pb free and Halogen free
high performance PC applications.
Tableꢀ1.ꢀOrderingꢀInformationꢀ
Part Number
Orgꢀ
MaxClock (MHz)
143 MHz
Package
Temperatureꢀ
AS4C64M4SA-7TCN
Commercial 0°C to +70°C
64Mx4
64Mx4
54-pin TSOPII
54-pin TSOPII
AS4C64M4SA-6TIN
166 MHz
Industrial -40°C to +85°C
Table 2. Key Specifications
-6
6
Unit
ns
AS4C64M4SA
-7
7
tCK3 Clock Cycle time(min.)
tAC3 Access time from CLK (max.)
tRAS Row Active time(min.)
5
5.4
42
63
ns
42
60
ns
ns
tRC
Row Cycle time(min.)
Confidential
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Rev.1.0 June 2017