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AS4C8M16S-6TAN PDF预览

AS4C8M16S-6TAN

更新时间: 2024-11-25 00:58:31
品牌 Logo 应用领域
ALSC /
页数 文件大小 规格书
55页 1214K
描述
Programmable Mode registers

AS4C8M16S-6TAN 数据手册

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AS4C8M16S  
128M - 8M x 16 bit Synchronous DRAM (SDRAM)  
Confidential  
Features  
(Rev. 2, Feb. /2014)  
Overview  
Fast access time from clock: 5/5.4 ns  
Fast clock rate: 166/143 MHz  
Fully synchronous operation  
Internal pipelined architecture  
2M word x 16-bit x 4-bank  
Programmable Mode registers  
- CAS Latency: 2, or 3  
- Burst Length: 1, 2, 4, 8, or full page  
- Burst Type: Sequential or Interleaved  
- Burst stop function  
The 128Mb SDRAM is  
a
high-speed CMOS  
synchronous DRAM containing 128 Mbits. It is  
internally configured as 4 Banks of 2M word x 16  
DRAM with a synchronous interface (all signals are  
registered on the positive edge of the clock signal,  
CLK). Read and write accesses to the SDRAM are  
burst oriented; accesses start at a selected location  
and continue for a programmed number of locations  
in a programmed sequence. Accesses begin with the  
registration of a BankActivate command which is then  
followed by a Read or Write command.  
Auto Refresh and Self Refresh  
4096 refresh cycles/64ms  
CKE power down mode  
The SDRAM provides for programmable Read or  
Write burst lengths of 1, 2, 4, 8, or full page, with a  
burst termination option. An auto precharge function  
may be enabled to provide a self-timed row precharge  
that is initiated at the end of the burst sequence. The  
refresh functions, either Auto or Self Refresh are easy  
to use. By having a programmable mode register, the  
system can choose the most suitable modes to  
maximize its performance. These devices are well  
suited for applications requiring high memory  
bandwidth and particularly well suited to high  
performance PC applications.  
Single +3.3V 0.3V power supply  
Interface: LVTTL  
Operating temperature range  
- Commercial (0 ~ 70°C)  
- Industrial (-40 ~ 85°C)  
- Automotive A2 (-40 ~ 105°C)  
54-pin 400 mil plastic TSOP II package  
54-ball 8.0 x 8.0 x 1.2mm (max) FBGA package  
All parts ROHS Compliant  
Table 1. Key Specifications  
AS4C16M16S  
-6/7  
tCK3  
tAC3  
tRAS  
tRC  
Clock Cycle time (min.)  
Access time from CLK (max.)  
Row Active time (min.)  
Row Cycle time (min.)  
6/7 ns  
5.4/5.4 ns  
42/42 ns  
60/63 ns  
Table 2. Ordering Information  
Part Number  
Frequency  
143 MHz  
166 MHz  
166 MHz  
166 MHz  
143 MHz  
166 MHz  
Package  
AS4C8M16S-7TCN  
AS4C8M16S-6TCN  
AS4C8M16S-6TIN  
54 pin TSOP II  
54 pin TSOP II  
54 pin TSOP II  
54 ball TFBGA  
54 ball TFBGA  
54 pin TSOP II  
AS4C8M16S-6BIN  
AS4C8M16S-7BCN  
AS4C8M16S-6TAN  
T : indicates TSOP II package  
B : indicates TFBGA package  
N : indicates Pb free and Halogen free ROHS compliant parts  
C: Commercial I: Industrial A: Automotive temperatures  
Confidential  
1
Rev. 2  
Feb. /2014  

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