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AS4C256K16F0-25JI PDF预览

AS4C256K16F0-25JI

更新时间: 2024-02-25 03:38:13
品牌 Logo 应用领域
ALSC 动态存储器
页数 文件大小 规格书
25页 518K
描述
5V 256K X 16 CMOS DRAM (Fast Page Mode)

AS4C256K16F0-25JI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:TSOP2, TSOP40/44,.46,32
针数:44Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.87Is Samacsys:N
访问模式:FAST PAGE最长访问时间:25 ns
其他特性:RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESHI/O 类型:COMMON
JESD-30 代码:R-PDSO-G40JESD-609代码:e0
长度:18.41 mm内存密度:4194304 bit
内存集成电路类型:FAST PAGE DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:40字数:262144 words
字数代码:256000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP40/44,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE峰值回流温度(摄氏度):240
电源:5 V认证状态:Not Qualified
刷新周期:512座面最大高度:1.2 mm
自我刷新:YES最大待机电流:0.0006 A
子类别:DRAMs最大压摆率:0.2 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10.16 mm
Base Number Matches:1

AS4C256K16F0-25JI 数据手册

 浏览型号AS4C256K16F0-25JI的Datasheet PDF文件第3页浏览型号AS4C256K16F0-25JI的Datasheet PDF文件第4页浏览型号AS4C256K16F0-25JI的Datasheet PDF文件第5页浏览型号AS4C256K16F0-25JI的Datasheet PDF文件第7页浏览型号AS4C256K16F0-25JI的Datasheet PDF文件第8页浏览型号AS4C256K16F0-25JI的Datasheet PDF文件第9页 
AS4C256K16FO  
®
Refresh cycle  
(V = 5V 10%, GND = 0V, T = 0° C to +70° C)  
CC a  
–25  
–30  
–35  
–50  
Standard  
Symbol  
Parameter  
Min  
10  
7
Max Min Max Min Max Min Max Unit  
Notes  
tCSR  
tCHR  
tRPC  
CAS setup time (CAS-before-RAS)  
CAS hold time (CAS-before-RAS)  
RAS precharge to CAS hold time  
10  
7
10  
8
10  
10  
0
ns  
ns  
ns  
3
3
0
0
0
CAS precharge time  
(CAS-before-RAS counter test)  
tCPT  
8
8
8
8
ns  
Output enable  
(V = 5V 10%, GND = 0V, T = 0° C to +70° C)  
CC a  
–25  
–30  
–35  
–50  
Standard  
Symbol  
Parameter  
Min Max Min Max Min Max Min Max Unit  
Notes  
tROH RAS hold time referenced to OE  
5
5
5
8
6
5
5
8
10  
5
5
8
10  
5
8
8
10  
ns  
ns  
ns  
ns  
ns  
tOEA  
tOED  
tOEZ  
tOEH  
OE access time  
OE to data delay  
Output buffer turnoff delay from OE  
OE command hold time  
8
8
8
8
Self refresh cycle  
(V = 5V 10%, GND = 0V, T = 0° C to +70° C)  
CC  
a
–25  
–30  
–35  
–50  
Standard  
Symbol  
Parameter  
Min  
Max Min Max Min Max Min Max Unit  
Notes  
tRASS RAS pulse width (CBR self refresh)  
100K  
RAS precharge time (CBR self refresh) 85  
100K  
85  
100K  
85  
100K  
85  
ns  
ns  
ns  
tRPS  
tCHS CAS hold time (CBR self refresh)  
30  
30  
30  
30  
Notes  
1
2
3
I
, I , I , and I  
depend on cycle rate.  
CC6  
CC1 CC3 CC4  
I
and I  
depend on output loading. Specified values are obtained with the output open.  
CC4  
CC1  
An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal  
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended  
periods of bias without clocks (greater than 8 ms).  
4
AC characteristics assume t = 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, V (min) GND and V (max) ≤  
T IL IH  
V
V
.
CC  
5
6
(min) and V (max) are reference levels for measuring timing of input signals. Transition times are measured between V and V .  
IL IH IL  
IH  
Operation within the t  
(max) limit insures that t  
(max) can be met. t  
(max) is specified as a reference point only. If t  
is greater than the speci-  
RCD  
RAC  
RCD  
RCD  
fied t  
(max) limit, then access time is controlled exclusively by t  
.
RCD  
CAC  
7
Operation within the t  
(max) limit insures that t  
(max) can be met. t  
RAC  
(max) is specified as a reference point only. If t  
is greater than the speci-  
RAD  
RAD  
RAD  
fied t  
(max) limit, then access time is controlled exclusively by t .  
AA  
RAD  
8
Assumes three state test load (5 pF and a 380 Thevenin equivalent).  
Either t or t must be satisfied for a read cycle.  
9
RCH  
RRH  
10  
11  
t
t
t
(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels.  
OFF  
, t  
, t  
, t  
and t  
are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If t  
WS  
WCS WCH RWD CWD  
AWD  
(min) and t  
t  
(min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If t  
WS  
WH  
W
H
R
W
D
t  
(min), t  
t  
(min) and t  
t  
(min), the cycle is a read-write cycle and the data out will contain data read from the selected cell. If  
AWD  
RWD  
CWD  
CWD  
AWD  
neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.  
12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.  
13 Access time is determined by the longest of t or t or t  
.
CAP  
CAA  
CAC  
14  
t
t to achieve t (min) and t  
(max) values.  
CAP  
ASC  
CP  
PC  
15 These parameters are sampled, but not 100% tested.  
4/11/01; V.0.9.1  
Alliance Semiconductor  
P. 6 of 25  

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