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AS4C256K16E0-35JC PDF预览

AS4C256K16E0-35JC

更新时间: 2024-01-01 10:32:02
品牌 Logo 应用领域
ALSC 存储内存集成电路光电二极管动态存储器
页数 文件大小 规格书
24页 632K
描述
5V 256Kx16 CMOS DRAM (EDO)

AS4C256K16E0-35JC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOJ包装说明:SOJ, SOJ40,.44
针数:40Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.69Is Samacsys:N
访问模式:FAST PAGE WITH EDO最长访问时间:35 ns
其他特性:RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESHI/O 类型:COMMON
JESD-30 代码:R-PDSO-J40JESD-609代码:e0
长度:26.0985 mm内存密度:4194304 bit
内存集成电路类型:EDO DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:40字数:262144 words
字数代码:256000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装等效代码:SOJ40,.44封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):225
电源:5 V认证状态:Not Qualified
刷新周期:512座面最大高度:3.76 mm
自我刷新:YES最大待机电流:0.001 A
子类别:DRAMs最大压摆率:0.19 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10.16 mm
Base Number Matches:1

AS4C256K16E0-35JC 数据手册

 浏览型号AS4C256K16E0-35JC的Datasheet PDF文件第4页浏览型号AS4C256K16E0-35JC的Datasheet PDF文件第5页浏览型号AS4C256K16E0-35JC的Datasheet PDF文件第6页浏览型号AS4C256K16E0-35JC的Datasheet PDF文件第8页浏览型号AS4C256K16E0-35JC的Datasheet PDF文件第9页浏览型号AS4C256K16E0-35JC的Datasheet PDF文件第10页 
AS4C256K16E0  
®
Notes  
1
2
3
I
, I , I , and I  
depend on cycle rate.  
CC6  
CC1 CC3 CC4  
I
and I  
depend on output loading. Specified values are obtained with the output open.  
CC1  
CC4  
An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal  
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after  
extended periods of bias without clocks (greater than 8 ms).  
4
AC Characteristics assume t = 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 60 pF, V (min) GND and V (max)  
T
IL  
IH  
V  
.
CC  
5
6
V
(min) and V (max) are reference levels for measuring timing of input signals. Transition times are measured between V and V .  
IH  
IL  
IH  
IL  
Operation within the t  
(max) limit insures that t  
(max) can be met. t  
(max) is specified as a reference point only. If t  
is greater than the  
RCD  
RAC  
RCD  
RCD  
specified t  
(max) limit, then access time is controlled exclusively by t  
.
CAC  
RCD  
7
Operation within the t  
(max) limit insures that t  
(max) can be met. t (max) is specified as a reference point only. If t  
RAD  
is greater than the  
RAD  
RAC  
RAD  
specified t  
(max) limit, then access time is controlled exclusively by t .  
AA  
RAD  
8
Assumes three state test load (5 pF and a 380 Thevenin equivalent).  
Either t or t must be satisfied for a read cycle.  
9
RCH  
RRH  
10  
11  
t
t
(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels.  
OFF  
, t  
, t  
, t  
and t  
are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If tWS t  
AWD WS  
WCS WCH RWD CWD  
(min) and t t (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If t  
t  
WH  
WH  
RWD  
(min), tCWD t  
(min) and tAWD t (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell.  
RWD  
CWD  
AWD  
If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.  
12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.  
13 Access time is determined by the longest of t or t or t  
.
CAP  
CAA  
CAC  
14  
t
ASC t to achieve t (min) and t  
(max) values.  
CP  
PC  
CAP  
15 These parameters are sampled and not 100% tested.  
Key to switching waveform  
Undefined/don’t care  
Rising input  
Falling input  
Read cycle waveform  
tRC  
tRAS  
tRCD  
tRSH  
tRP  
RAS  
tCSH  
tASC  
tRCS  
tCAH  
tCRP  
tCAS  
UCAS,  
tAR  
LCAS  
tRAD  
tRAL  
tASR  
tRAH  
Row Address  
Address  
Col Address  
tRRH  
tRCH  
WE  
OE  
tROH  
tOEZ  
tRAC  
tAA  
tOFF  
tOEA  
tCAC  
tCLZ  
Data Out  
I/O  
4/11/01; v.1.1  
Alliance Semiconductor  
7 of 24  

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