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AS3665-ZWLT PDF预览

AS3665-ZWLT

更新时间: 2024-02-13 21:41:20
品牌 Logo 应用领域
艾迈斯 - AMSCO 驱动器
页数 文件大小 规格书
78页 3331K
描述
9 Channel Advanced Command Driven RGB/White LED Driver

AS3665-ZWLT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:FBGA, BGA25,5X5,20Reach Compliance Code:unknown
风险等级:5.82Is Samacsys:N
JESD-30 代码:S-PBGA-B25端子数量:25
最高工作温度:85 °C最低工作温度:-30 °C
封装主体材料:PLASTIC/EPOXY封装代码:FBGA
封装等效代码:BGA25,5X5,20封装形状:SQUARE
封装形式:GRID ARRAY, FINE PITCH电源:3/5 V
认证状态:Not Qualified子类别:Display Drivers
表面贴装:YES温度等级:OTHER
端子形式:BALL端子节距:0.5 mm
端子位置:BOTTOMBase Number Matches:1

AS3665-ZWLT 数据手册

 浏览型号AS3665-ZWLT的Datasheet PDF文件第4页浏览型号AS3665-ZWLT的Datasheet PDF文件第5页浏览型号AS3665-ZWLT的Datasheet PDF文件第6页浏览型号AS3665-ZWLT的Datasheet PDF文件第8页浏览型号AS3665-ZWLT的Datasheet PDF文件第9页浏览型号AS3665-ZWLT的Datasheet PDF文件第10页 
AS3665  
Datasheet, Confidential - Electrical Characteristics Pin Description  
Table 3. Electrical Characteristics (Continued)  
Symbol  
Parameter  
Condition  
Min  
Typ  
Max  
Unit  
ADC temperature  
measurement offset  
value  
ADCTOFFSE  
T
393  
ºC  
Code temperature  
coefficient  
ºC/  
Code  
ADCTC  
1.322  
Temperature sensor  
accuracy  
TTOL  
-10  
+10  
ºC  
Audio Input  
pin INT/AUDIO_IN if used as analog input;  
at maximum input gain (+30dB)  
RAUDIO_IN Audio Input resistance  
20  
kΩ  
Digital Interface  
High Level Input  
VIH  
1.26  
0.0  
VVBAT  
0.54  
0.2  
V
V
Voltage  
Pins SDA, SCL, EN, CLK32K, TRIG,  
INT/AUDIO_IN, GPO1  
Low Level Input  
VIL  
Voltage  
Pins SDA, TRIG, INT/UDIOIN, GPO  
IOL=3mA  
Low Level Output  
VOL  
V
Voltage  
Pins SDA, SCL, , CLK32K, TRIG, INT/  
AUDGPO  
ILEAK  
Leakage Current  
0.01  
1.0  
µA  
I2C mode timings - see Figure 3 on page 7  
fSCLK  
SCL Clock Frequency  
0
400  
kHz  
µs  
Bus Free Time  
Between a STOP and  
START Condition  
tBUF  
1.3  
Hold Time (Repeated)  
START Condition2  
tHD:STA  
0.6  
µs  
LOW Period of SCL  
Clock  
tLOW  
tHIGH  
1.3  
0.6  
µs  
µs  
HIGH Period of SCL  
Clock  
Setup Time for a  
Repeated START  
Condition  
tSU:STA  
0.6  
µs  
Data Hold Time3  
Data Setup Tim4  
tHD:DAT  
tSU:DAT  
tR  
tF  
tSU:STO  
CB  
0
0.9  
µs  
ns  
100  
20 +  
0.1CB  
Rise Timof Both  
SDA and SCSignals  
300  
300  
ns  
ns  
µs  
pF  
pF  
20 +  
0.1CB  
Fall me of Both SDA  
and CL Signals  
Setup Time for STOP  
Condition  
0.6  
Capacitive Load for  
Each Bus Line  
CB — total capacitance of one bus line in pF  
400  
10  
I/O Capacitance  
(SDA, SCL)  
CI/O  
If SCL and SDA are low for longer than this  
time, the AS3665 is switched into shutdown  
I2C timeout  
tTIMEOUT  
100  
ms  
mode5  
www.austriamicrosystems.com  
Revision 1.0.2  
6 - 77  

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