FLASH
AS29F040
TM
Autoselect Command Sequence
Chip Erase Command Sequence
The autoselect command sequence allows the host
Chip erase is a six-bus-cycle operation. The chip erase
system to access the manufacturer and devices codes, and command sequence is initiated by writing two unlock cycles,
determine whether or not a sector is protected. The Command followed by a set-up command. Two additional unlock write
Definitions table shows the address and data requirements. cycles are then followed by the chip erase command, which
This method is an alternative to that shown in the Autoselect in turn invokes the Embedded Erase algorithm. The device
Codes (High Voltage Method) table, which is intended for PROM does not require the system to preprogram prior to erase. The
programmers and requires VID on address bit A9.
Embedded Erase algorithm automatically pre-programs and
The auto select command sequence is initiated by writing verifies the entire memory for an all zero data pattern prior to
two unlock cycles, followed by the autoselect command. The electrical erase. The system is not required to provide any
device then enters the autoselect mode, and the system may controls or timings during these operations. The Command
read at any address any number of times, without initiating Definitions table shows the address and data requirements for
another command sequence.
the chip erase command sequence.
A read cycle at address XX00h retrieves the manufacturer
Any commands written to the chip during the Embedded
code. A read cycle at address XX01h returns the device Erase algorithm are ignored.
code. A read cycle containing a sector address (SA) and the
The system can determine the status of the erase
address 02h in returns 01h if that sector is protected, or 00h operation by using DQ7, DQ6, or DQ2 (see “Write Operation
if it is unprotected (refer to the Sector Address tables for valid Status” for information on these status bits). When the
sector addresses).
Embedded Erase algorithm is complete, the device returns to
The system must write the reset command to exit the reading array data and addresses are no longer latched.
autoselect mode and return to reading array data.
Figure 2 illustrates the algorithm for the erase
operation. See the Erase/Program Operations tables in “AC
Characteristics” for parameters and the Chip /Sector Erase
Operation Timings for timing waveforms.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in turn
initiate the Embedded Program algorithm. The system is not
required to provide further controls or timings. The device
automatically provides internally generated program pulses and
verify the programmed cell margin. The Command Definitions
take shows the address and data requirements for the byte
program command sequence.
FIGURE 1: PROGRAM OPERATION
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses are
no longer latched. The system can determine the status of the
program operation by using DQ7 or DQ6. See “Write Operation
Status” for information on these status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from a “0”
back to a “1”. Attempting to do so may halt the operation and
set DQ5 to “1”, or cause the Data\ Polling algorithm to indicate
the operation was successful. However, a succeeding read
will show that the data is still “0”. Only erase operations can
convert a “0” to a “1”.
NOTE: See the appropriate Command Definitions table for program
command sequence.
Micross Components reserves the right to change products or specifications without notice.
AS29F040 • Rev. 3.1 07/19
7
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