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AS29F040-150TC PDF预览

AS29F040-150TC

更新时间： 2024-02-16 11:40:00
品牌 Logo 应用领域
ALSC 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
18页 325K
描述
5V 512K x 8 CMOS FLASH EEPROM

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AS29F040-150TC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSOP包装说明：TSOP1, TSSOP32,.8,20
针数：32Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.51
风险等级：5.37最长访问时间：150 ns
其他特性：10K WRITE/ERASE CYCLE ENDURANCE命令用户界面：YES
数据轮询：YES耐久性：10000 Write/Erase Cycles
JESD-30 代码：R-PDSO-G32JESD-609代码：e0
长度：18.4 mm内存密度：4194304 bit
内存集成电路类型：FLASH内存宽度：8
功能数量：1部门数/规模：8
端子数量：32字数：524288 words
字数代码：512000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：512KX8输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSOP1
封装等效代码：TSSOP32,.8,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE并行/串行：PARALLEL
电源：5 V编程电压：5 V
认证状态：Not Qualified座面最大高度：1.2 mm
部门规模：64K最大待机电流：0.0004 A
子类别：Flash Memories最大压摆率：0.06 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
切换位：YES类型：NOR TYPE
宽度：8 mmBase Number Matches：1

AS29F040-150TC 数据手册

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Item  
Description  
Initiate read or reset operations by writing the read/ reset command sequence into the command  
register. This allows the microprocessor to retrieve data from the memory. Device remains in read mode  
until command register contents are altered.  
Reset/ read  
Device automatically powers up in read/ reset state. This feature allows only reads, therefore ensuring no  
spurious memory content alterations during power up.  
AS29F040 provides manufacturer and device codes in two ways. External PROM programmers typically  
access the device codes by driving +12V on A9. AS29F040 also contains an ID read command to read  
the device code with only +5V, since multiplexing +12V on address lines is generally undesirable.  
Initiate device ID read by writing the ID read command sequence into the command register. Follow  
with a read sequence from address XXX00h to return MFG code. Follow ID read command sequence  
with a read sequence from address XXX01h to return device code.  
ID read  
To verify write protect status on sectors, read address XXX02h. Sector addresses A18–A16 produc e a1  
on DQ0 for protected sector and a 0 for unprotected sector.  
Exit from ID read mode with Read/ Reset command sequence.  
Programming the AS29F040 is a four bus cycle operation performed on a byte-by-byte basis. Two  
unlock write cycles precede the program setup command and program data write cycle. Upon  
execution of the program command, no additional CPU controls or timings are necessary. Addresses are  
latched on the falling edge of CE or WE, whichever is last; data is latched on the rising edge of CE or  
WE, whichever is first. The AS29F040’s automated on-chip program algorithm provides adequate  
internally-generated programming pulses and verifies the programmed cell margin.  
Check programming status by sampling data on the DATA polling (DQ7), or toggle bit (DQ6). The  
AS29F040 returns the equivalent data that was written to it (as opposed to complemented data), to  
complete the programming operation.  
Byte/ word  
programming  
The AS29F040 ignores commands written during the programming operation.  
AS29F040 allows programming in any sequence, across any sector boundary. Changing data from 0 to 1  
requires an erase operation. Attempting to program data 0 to 1 results in DQ5 = 1 (exceeded  
programming time limits); reading this data after a read/ reset operation returns a 0. When  
programming time limit is exceeded, DQ5 reads high, and DQ6 continues to toggle. In this state , areset  
command returns the device to read mode.  
Chip erase requires six bus cycles: two unlock write cycles; a setup command, two additional unlock  
write cycles; and finally the Chip erase command.  
Chip erase does not require logical 0s to be written prior to erasure. When the automated on-chip erase  
algorithm is invoked with the Chip erase command sequence, AS29F040 automatically programs and  
verifies the entire memory array for an all-zero pattern prior to erase. The AS29F040 returns to read  
mode upon completion of chip erase unless DQ5 is set high as a result of exceeding time limit.  
Chip erase  
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