Data Sheet AS1500/1/2/3
AS1502 / AS1503 – SPECIFICATIONS
VDD = 3V±10% or 5V±10%, VA = VDD, VB = 0V, –40°C ≤ TA ≤ +125°C unless otherwise noted.
ELECTRICAL CHARACTERISTICS – 50k and 100k VERSIONS
Parameter
Symbol
Conditions
Min Typ12 Max
Unit
DC CHARACTERISTICS RHEOSTAT MODE
40
80
50
60
TA = 25°C, VDD = 5V, AS1502, Version: 50kΩ
TA = 25°C, VDD = 5V, AS1503, Version: 100kΩ
VAB = VDD, Wiper = No Connect
VDD = 5V
kΩ
kΩ
Nominal Resistance13
RAB
100
500
100
±1/4
±1/2
120
Resistance Tempco14
Wiper Resistance
ppm/°C
Ω
∆RAB/∆T
RW
20
–1
–2
200
+1
Resistor Differential NL15
Resistor Integral NL
R-DNL RWB, VDD = 5V, VA = No Connect
LSB
R-INL
RWB, VDD = 5V, VA = No Connect
+2
LSB
DC CHARACTERISTICS POTENTIOMETER DIVIDER
Resolution
N
8
±1
Bits
LSB
VDD = 5.5V TA = 25°C
VDD = 2.7V TA = 25°C
VDD = 5.5V TA = 25°C
VDD = 2.7V TA = 25°C
Code = 80H
–4
–4
–1
–1
+4
+4
+1
+1
Integral Nonlinearity
INL
±1
LSB
±1/4
±1/4
15
LSB
Differential Nonlinearity
DNL
LSB
Voltage Divider Tempco
Full-Scale Error
ppm/°C
LSB
∆VW /∆T
VWFSE
Code = FFH, VDD = 5.5V
Code = 00H, VDD = 5.5V
–1
0
–0.25
0.1
0
1
Zero-Scale Error
VWZSE
LSB
RESISTOR TERMINALS
Voltage Range16
VA, B, W
CA, B
CW
0
VDD
V
Capacitance17 Ax, Bx
Capacitance Wx
f = 1MHz, Measured to GND, Code = 80H
f = 1MHz, Measured to GND, Code = 80H
15
80
pF
pF
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
VIH
VDD = 5V
2.4
2.1
V
V
VIL
VIH
VDD = 5V
0.8
Input Logic High
Input Logic Low
VDD = 3V
V
VIL
VDD = 3V
0.6
±1
V
Input Current
IIH, IIL
CIL
VIN = 5V or 0V, VDD = 5V
µA
pF
Input Capacitance
POWER SUPPLIES
Power Supply Range
Supply Current (CMOS)
Supply Current (TTL)18
Power Dissipation
(CMOS)19
5
VDD
IDD
IDD
2.7
5.5
1
V
VIH = VDD or VIL = 0V, VDD = 5.5V
VIH = 2.4V or 0.8V, VDD = 5.5V
0.1
0.9
µA
mA
4
PDISS
VIH = VDD or VIL = 0V, VDD = 5.5V
27.5
tbd.
tbd.
µW
dB
-43
-48
AS1502, Version: 50kΩ
Power Supply Suppression
Ratio
VDD = 5V + 0.5VP
sine wave @ 1kHz
PSSR
AS1503, Version:
dB
100kΩ
DYNAMIC CHARACTERISTICS20
BW_50k
220
110
kHz
kHz
%
RWB = 50kΩ, VDD = 5V
Bandwidth –3dB
Bandwidth –3dB
BW_100k
THDW
RWB = 100kΩ, VDD = 5V
VA = 1VRMS + 2VDC, VB = 2VDC, f = 1kHz
RWB = 50kΩ, VA = VDD, VB = 0V, ±1% Error
Band
Total Harmonic Distortion
0.003
tS_50k
9
µs
VW Settling Time
RWB = 100kΩ, VA = VDD, VB = 0V, ±1% Error
Band
RWB = 50kΩ, f = 1kHz
tS_100k
18
20
29
µs
eNWB_50k
eNWB_100
k
nV/ √ Hz
nV/ √ Hz
Resistor Noise Voltage
RWB = 100kΩ, f = 1kHz
Table 4: Electrical Characteristics – 50k and 100k Versions
12
Typicals represent average readings at 25°C and VDD = 5V.
13
Wiper is not connected. IAB = 70µA for the 50kΩ version and 35µA for the 100kΩ version.
14
All Tempcos are guaranteed by design and not subject to production test.
15
Terminal A is not connected. IW = 70µA for the 50kΩ version and 35µA for the 100kΩ version.
16
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
17
All capacitances are guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5V
bias on the measured terminal. The remaining resistor terminals are left open circuit.
18
19
20
Worst-case supply current consumed when input logic level at 2.4V, standard characteristic of CMOS logic.
PDISS is calculated from (IDD×VDD). CMOS logic level inputs result in minimum power dissipation.
All dynamic characteristics are guaranteed by design and not subject to production test. All dynamic characteristics use VDD=5V.
Revision 1.0, Oct 2004
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