Datasheet > AS1160

AS1160

更新时间： 2022-10-11 11:45:13

品牌	Logo	应用领域
艾迈斯 - AMSCO		/
页数	文件大小	规格书
29页	902K
描述
20MHz - 66MHz, 10-Bit Bus, IEEE 1149.1 (JTAG) Compliant LVDS Serializer/Deserializer

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

AS1160 数据手册

AS1160/AS1161

Datasheet - Application Information

PCB Considerations

The serializer and deserializer should be placed as close to the PCB edge connector as possible. In multiple deserial-

izer applications, the distance from the deserializer to the slot connector appears as a stub to the serializer driving the

backplane traces. Longer stubs lower the impedance of the bus, increase the load on the serializer and lower the

threshold margin at the deserializers. Deserializer devices should be placed much less than one inch from slot connec-

tors. Because transition times are very fast on the serializer bus LVDS outputs, reducing stub lengths as much as pos-

sible is the best method to ensure signal integrity.

For bus LVDS applications the LVTTL, LVCMOS and bus LVDS signals should be separated from each other to pre-

vent coupling into the bus lines. This can be achieved by using a four-layer PCB where the power, ground and input/

output signals are separated.

Transmission Media

The transmission line characteristics affect the performance of the AS1160/AS1161. It’s recommended to use con-

trolled-impedance media and to terminate at both ends of the transmission line (see Figure 37). Twisted pair cables

should be used due to their superior signal quality and the less EMI generation. Noise which is picked up as common

mode in the twisted pair is rejected by the differential receiver.

It’s important to eliminate reflections and to run the differential traces as close together as possible to ensure that the

noise is coupled as common mode. Also take care of matching the electrical length of the traces to prevent a degrada-

tion of the magnetic field cancellation. To avoid an external magnetic field, the differential output signals should also be

placed as close together as possible.

The potential of offsetting the ground levels of the serializer vs. the deserializer must be considered. The bus LVDS

provides a +1.2V common mode range at the receiver inputs.

Figure 37. Double-Terminated Point-to-Point

Serialized Data

DO+

DO-

RI+

RI-

10-bit

Parallel

Data Out

Parallel

Data In

56Ω

AS1161

AS1160

Strip Line or Twisted Pair

Z = 28Ω

The serializer/deserializer chipset can be used in many different topologies. Such as multidrop configurations (see Fig-

ure 35 on page 20), through a PCB trace or through twisted pair cable (see Figure 37).

In point-to-point configurations, it’s possible to terminated the transmission line only once at the receiver end. With only

one termination the reflections and the differential signal swing are larger compared to a double termination.

www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61

Revision 1.01

24 - 29

1...21 22 232425 26 27...29

中文翻译

下载PDF

与AS1160相关器件

型号	品牌	获取价格	描述	数据表
AS1160-BCTT	AMSCO	获取价格	20MHz - 66MHz, 10-Bit Bus, IEEE 1149.1 (JTAG) Compliant LVDS Serializer/Deserializer
AS11619	SUMIDA	获取价格	LF Transmitter Antenna
AS11619-125A	SUMIDA	获取价格	LF Transmitter Antenna
AS11619-125B	SUMIDA	获取价格	LF Transmitter Antenna
AS11619-125C	SUMIDA	获取价格	LF Transmitter Antenna
AS11619-125D	SUMIDA	获取价格	LF Transmitter Antenna
AS11619-125E	SUMIDA	获取价格	LF Transmitter Antenna
AS11619-134A	SUMIDA	获取价格	LF Transmitter Antenna
AS11619-134B	SUMIDA	获取价格	LF Transmitter Antenna
AS11619-134C	SUMIDA	获取价格	LF Transmitter Antenna

与AS1160相关文章

压敏电阻器在直流电路中的过压保护应用探讨
2024-06-07

2
电感耐压值及其与电感大小的关系
2024-06-07

5
CNY17F光耦合器：特性、应用、封装、引脚功能及替换型号解析
2024-06-07

4
DS1307资料解析：特性、引脚说明、替代推荐
2024-06-07

3

产品中心

服务支持

精选活动

关于我们

帮助中心

AS1160

AS1160 数据手册

与AS1160相关器件

与AS1160相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AS1160

AS1160 数据手册

与AS1160相关器件

与AS1160相关文章

您还可以找

您在本页遇到什么问题？