APU0065 PRELIMINARY
PIN DESCRIPTION-QFP100
INPUT/
NAME
PAD (NO.)
DESCRIPTION
INTERFACE
OUTPUT
VEE (33)
Power
Power
Power
Input
Negative Supply Voltage
Operating Voltage
Operating Voltage
Bias Voltage
For LCD driver circuit(0
For logical circuit (+5V
V
V
DD -10V)
Power Supply
Power Supply
Power Supply
Power Supply
≥
≥
EE
V
D D (25)
SS (36)
10%, +3V
10%)
±
±
V
0V (GND)
V1 ~ V6
(46 ~ 51)
Bias Voltage level for LCD drive
This is the signal for LCD twisting
Altemated signal for LCD
driver output
Input
Input
Controller
Controller
M (42)
CL1, CL2
(34, 35)
These signal control the shift and latch of
driver. More detail scription in next lineFCS
Data shift / latch clock
.
If FCS equals to VSS , Part1 and Part2 both are segment mode.
If FCS equals to VDD , Part1 is segment mode but Part2 is
common mode .
Mode
CL1
CL2
M
Mode selection
FCS (45)
Controller
Input
latch
shift
Segment
M
Common
M
shift
latch
Selection of the shift directon of Part 1 shift register
SHL1
VD D
DL1
output
input
DR1
input
Shifting direction control
signal of Part1
Controller
SHL1 (43)
Input
VSS
output
Controller
or
APU0063
DL1, DR1
(37, 38)
Input
Output
Data interface
LCD driver
Data input / output of Part1 shift register
LCD driver output of Part1
SC1 ~ SC20
Output
LCD
Selection of the shift directon of Part 2 shift register
SHL2
VD D
DL2
DR2
Input
output
Shifting direction control
signal of Part2
SHL2 (44)
Input
Controller
output
Input
VSS
Controller
or
APU0063
Input
Output
DL2, DR2
(39, 40)
Data interface
LCD driver
Data input / output of Part 2 shift register
LCD driver output of Part2
SC21 ~ SC40
Output
LCD
Note : Input pin can not be floated, or it will cause large leakage current.
Copyright ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002
3
www.anpec.com.tw