APU0063 PRELIMINARY
MAXIMUM ABSOLUTE LIMIT (Ta = 25 °C)
Unit
Characteristic
Operating Voltage
Driver Supply Voltage
Input Voltage 1
Symbol
V DD
Value
- 0.3 ~ + 7.0
V
V LCD
V IN1
V DD - 13.5 ~ VDD + 0.3
- 0.3 ~ VDD + 0.3
V
V
Input Voltage 2 (V~V4)
V IN2
V DD + 0.3 ~ V - 0.3
V
E E
1
Operating Temperature
Storage Temperature
TOPR
- 30 ~ + 85
oC
oC
TSTG
- 55 ~ + 125
Voltage greater than above may damage to the circuit
ELECTRICAL CHARACTERISTICS
DC characteristics (VDD = 2.7 ~ 5.5V, 0 ≥ VEE ≥ VDD - 10V, VSS = 0V, Ta = - 30 ~ + 85 °C )
Test condition
Characteristic
Operating Current*
Supply Current*
Symbol
Applicable pin
Min
_
Max
Unit
IDD
fCL2 = 400 KHz
1
mA
_
_
IEE
VIH
VIL
fCL1 = 1 KHz
10
µ
A
VDD
Input High Voltage
0.7 VDD
0
_
V
CL1, CL2, DR1, DR2,
DR1, DR2, SHL1, SHL2,
M, FCS
0.3 VDD
Input Low Voltage
ILKC
VOH
VOL
VD1
VD2
V
IN = 0 - VDD
5
_
-5
VDD - 0.4
_
A
µ
Input Leakage Current
Output High Voltage
IOH = -0.4 mA
IOL = +0.4 mA
DL1, DL2, DR1, DR2
0.4
1.1
1.5
Output Low Voltage
Voltage Descending
V
_
_
ION = 0.1mA for one of SC1-SC80
V (V1 ~ V4) -
SC (SC1 ~ SC80)
I
ON = 0.05mA for each SC1-SC80
V
IN = VDD ~ VEE
Leakage Current
IV
-10
10
V1 ~ V4
µ
A
(Output SC1 ~ SC80 : floating)
AC CHARACTERISTICS (VDD = 2.7 ~ 5.5V, 0 ≥ VEE ≥ VDD - 10V, VSS = 0V, Ta= - 30 ~ + 85 °C )
Test condition
Characteristic
Data shift Frequency
Clock High Level Width
Clock Low Level Width
Symbol
Applicable pin
CL2
Min
Max
Unit
_
_
fCL
400
KHz
_
_
tW C K H
tW C K L
tSL
800
800
500
CL1, CL2
_
_
_
_
_
CL2
from CL2 to CL1
Clock Set-up Time
tLS
from CL1 to CL2
_
500
_
CL1, CL2
ns
tR / tF
tSU
Clock Rise/Fall Time
Data Set-up Time
Data Hold Time
200
_
_
_
300
DL1, DL2, DR1, DR2, FLM
DL1, DL2, DR1, DR2
_
tDH
300
_
tD
Data Delay Time
CL1=15pF
500
Copyright ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002
6
www.anpec.com.tw