Datasheet > AOZ5019QI

AOZ5019QI

更新时间： 2022-02-26 12:46:18

品牌	Logo	应用领域
美国万代 - AOS		服务器主板节能技术
页数	文件大小	规格书
13页	616K
描述
High-Current, High-Performance DrMOS Power Module

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数据手册

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AOZ5019QI 数据手册

AOZ5019

Pin Description

Pin Number

Pin Name

Pin Function

SMOD

Skip Mode input. When the pin is held active low, Diode Emulation or Skip Mode is enabled for

the LS FET.

VCC

Control and Driver supply input. Nominal 5 V.

BOOT

Gate drive supply for the HS FET. Nominal 5 V. The bootstrap diode is internal to the module.

Connect a 0.1 F or higher ceramic capacitor between VSWH node at pin 5.

Gate of the HS FET. Used for module testing during production. No user connections.

VSWH

Switching or phase node connected to source of high side MOSFET and drain of the low side

MOSFET. Electrically attached to the LS FET drain tab, this pin is dedicated for BOOT Cap

connection and needs to be connected to Pin 13 externally on PCB.

6, 7, 8

VIN

Power input to the switching MOSFETs. Attached to the HS FET drain tab.

Power ground.

9, 10, 11, 12,

17, 18

PGND

13, 14, 15, 16

VSWH

Switching or phase node connected to source of high side MOSFET and drain of the low side

MOSFET. Electrically attached to the LS FET drain tab.

CGND

VIN

Gate of the LS FET. Used for module testing during production. No user connections.

Control or analog ground for return of control signals and bypass capacitors.

Power input to the switching MOSFETs. Attached to the HS FET drain tab.

Disable pin for the controller. Both gates are held active low when EN is grounded.

Pulse Width Modulated Tri-State input from external controller.

PWM

Functional Block Diagram

VCC

BOOT

VIN

VCC

UVLO

PWM

VSWH

Shoot

Through

Control

Complementary

Control Logic

VCC

SMOD

PGND

CGND

Rev. 3.0 May 2018

www.aosmd.com

Page 3 of 13

1 234 5 6 7...13

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