Datasheet > AOZ5006

AOZ5006

更新时间： 2022-06-03 06:09:10

品牌	Logo	应用领域
美国万代 - AOS		电源电路服务器主板节能技术
页数	文件大小	规格书
16页	823K
描述
35A DrMOS Power Module

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数据手册

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AOZ5006 数据手册

AOZ5006

Pin Description

Pin Number

Pin Name

Pin Function

SMOD

Skip Mode input. When the pin is held active low, Diode Emulation or Skip Mode is enabled for

the LS FET.

VCIN

Control supply input. Nominal 5V. Can be derived from the gate drive supply VDRV with an RC

filter for noise bypass.

VDRV

BOOT

Gate drive supply input. Nominal 5V.

Gate drive supply for the HS FET. Nominal 5V. The bootstrap diode is internal to the module.

Connect a 0.1F or higher ceramic capacitor between VSWH node at pin 7.

5, 37

CGND

Control or analog ground for return of control signals and bypass capacitors.

Attached to exposed pad in the driver section.

Gate of the HS FET. Used for module testing during production. No user connections.

Switching or the phase node for bootstrap capacitor connection.

Power input to the switching MOSFETs. Attached to the HS FET drain tab.

Switching or the phase node pin. Not for power connections.

VSWH

VIN

8 to 14

VSWH

PGND

VSWH

16 to 28

29 to 35

Power ground. Internally connected to control GND of pin 37.

Switching or phase node connected to source of high side MOSFET and drain of the low side

MOSFET. Electrically attached to the LS FET drain tab.

Gate of the LS FET. Used for module testing during production. No user connections.

Open drain output of the thermal shutdown circuit. Active low.

THDN

DISB#

PWM

Disable pin for the controller. Both gates are held active low when DISB# is grounded.

Pulse Width Modulated Tri State input from external controller.

Functional Block Diagram

VDRV

VCIN

BOOT

VIN

PWM

VSWH

Shoot

Through

Control

Complementary

Control Logic

VDRV

DISB#

SMOD

THDN

CGND

PGND

Temp

SHDN

VCIN

UVLO

Rev. 1.5 April 2012

www.aosmd.com

Page 3 of 16

1 234 5 6 7...16

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