AN983B PCI/miPCI Fast Ethernet Controller with integrated PHY
CR13 (offset = 34h), CP - Capabilities Pointer. ............................................... 25
CR15 (offset = 3ch), CI - Configuration Interrupt............................................ 25
CR16 (offset = 40h), DS - Driver Space for special purpose. .......................... 25
CR32 (offset = 80h), SIG - Signature of AN983B ........................................... 25
CR48 (offset = c0h), PMR0, Power Management Register0............................ 26
CR49 (offset = c4h), PMR1, Power Management Register 1........................... 26
7.2. PCI Control/Status registers.............................................................................. 28
7.2.1. PCI Control/Status registers list........................................................... 28
7.2.2. Control/Status register description.......................................................... 29
CSR0 (offset = 00h), PAR - PCI Access Register............................................ 29
CSR1 (offset = 08h), TDR - Transmit demand register.................................... 30
CSR2 (offset = 10h), RDR - Receive demand register..................................... 30
CSR3 (offset = 18h), RDB - Receive descriptor base address ......................... 30
CSR5 (offset = 28h), SR - Status register......................................................... 30
CSR6 (offset = 30h), NAR - Network access register...................................... 32
CSR7 (offset = 38h), IER - Interrupt Enable Register...................................... 34
CSR8 (offset = 40h), LPC - Lost packet counter.............................................. 35
CSR9 (offset = 48h), SPR - Serial port register................................................ 35
CSR11 (offset = 58h), TMR -General-purpose Timer...................................... 36
CSR13 (offset = 68h), WCSR –Wake-up Control/Status Register................... 36
CSR14 (offset = 70h), WPDR –Wake-up Pattern Data Register...................... 37
CSR15 (offset = 78h), WTMR - Watchdog timer ............................................ 38
CSR16 (offset = 80h), ACSR5 - Assistant CSR5 (Status register 2)................ 39
CSR17 (offset = 84h), ACSR7- Assistant CSR7 (Interrupt enable register 2). 40
CSR18 (offset = 88h), CR - Command Register, bit31 to bit16....................... 40
CSR19 (offset = 8ch) - PCIC, PCI bus performance counter........................... 42
CSR20 (offset = 90h) - PMCSR, Power Management Command and Status.. 42
CSR21 (offset = 94h) - WTDP, The current working transmit descriptor pointer
........................................................................................................................... 43
CSR22 (offset = 98h) - WRDP, The current working receive descriptor pointer
........................................................................................................................... 43
CSR23 (offset = 9ch) - TXBR, transmit burst count / time-out........................ 43
CSR24 (offset = a0h) - FROM, Flash ROM (also the boot ROM) port........... 44
CSR25 (offset = a4h) - PAR0, physical address register 0............................... 44
Rev. 1.8
4
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